llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-clang-driver Author: Ramkumar Ramachandra (artagnon) <details> <summary>Changes</summary> Ascalon XG is the global variant of Ascalon X, to meet export restrictions: it lacks the Zvkng extension and has reduced vector FP64 throughput. Add it as tt-ascalon-xg to RISCVProcessors. Restructure the Ascalon scheduling model into a multiclass similar to the SiFive7 model, so that both cores share the same definitions. On Ascalon XG, vector instructions producing FP64 results (SEW=64 add/mul/fma, and the SEW=32 widening add/mul/fma and conversions) additionally occupy an FP64 unit for 4x the cycles and have increased latency. tt-ascalon-x is unchanged. Ref: https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=2bfe853b3b1703216a32a48d2bc61363140c6aea Assisted-by: llm -- 8< -- Kindly review this patch with whitespace changes turned off on GitHub. --- Patch is 104.85 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/229030.diff 6 Files Affected: - (modified) clang/test/Driver/riscv-cpus.c (+65) - (modified) clang/test/Misc/target-invalid-cpu-note/riscv.c (+2) - (modified) llvm/docs/ReleaseNotes.md (+3) - (modified) llvm/lib/Target/RISCV/RISCVProcessors.td (+39-30) - (modified) llvm/lib/Target/RISCV/RISCVSchedTTAscalonX.td (+914-843) - (added) llvm/test/tools/llvm-mca/RISCV/tt-ascalon-x/vfp64.s (+116) ``````````diff diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index 9cfe399ca71a7..9376492309cc0 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -250,6 +250,71 @@ // MCPU-TT-ASCALON-X-SAME: "-target-feature" "+svpbmt" // MCPU-TT-ASCALON-X-SAME: "-target-abi" "lp64d" +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=tt-ascalon-xg | FileCheck -check-prefix=MTUNE-TT-ASCALON-XG %s +// MTUNE-TT-ASCALON-XG: "-tune-cpu" "tt-ascalon-xg" + +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=tt-ascalon-xg | FileCheck -check-prefix=MCPU-TT-ASCALON-XG %s +// MCPU-TT-ASCALON-XG: "-target-cpu" "tt-ascalon-xg" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+m" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+a" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+f" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+d" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+c" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+v" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+h" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+zicbom" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+zicbop" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+zicboz" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+zicntr" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+zicond" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+zicsr" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+zifencei" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+zihintntl" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+zihintpause" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+zihpm" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+zimop" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+zmmul" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+zawrs" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+zfa" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+zfbfmin" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+zfh" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+zfhmin" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+zca" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+zcb" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+zba" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+zbb" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+zbs" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+zkr" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+zkt" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+zvbb" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+zvbc" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+zve32f" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+zve32x" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+zve64d" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+zve64f" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+zve64x" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+zvfbfmin" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+zvfbfwma" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+zvfh" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+zvfhmin" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+zvkb" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+zvkt" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+zvl128b" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+zvl256b" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+zvl32b" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+zvl64b" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+smaia" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+smmpm" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+smnpm" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+smrnmi" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+smstateen" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+sscofpmf" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+svinval" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+svnapot" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "+svpbmt" +// MCPU-TT-ASCALON-XG-SAME: "-target-feature" "-zvkng" +// MCPU-TT-ASCALON-XG-SAME: "-target-abi" "lp64d" + // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=xiangshan-nanhu | FileCheck -check-prefix=MTUNE-XIANGSHAN-NANHU %s // MTUNE-XIANGSHAN-NANHU: "-tune-cpu" "xiangshan-nanhu" diff --git a/clang/test/Misc/target-invalid-cpu-note/riscv.c b/clang/test/Misc/target-invalid-cpu-note/riscv.c index 86fdf400ac461..df13001fedf0d 100644 --- a/clang/test/Misc/target-invalid-cpu-note/riscv.c +++ b/clang/test/Misc/target-invalid-cpu-note/riscv.c @@ -60,6 +60,7 @@ // RISCV64-SAME: {{^}}, syntacore-scr5-rv64 // RISCV64-SAME: {{^}}, syntacore-scr7 // RISCV64-SAME: {{^}}, tt-ascalon-x +// RISCV64-SAME: {{^}}, tt-ascalon-xg // RISCV64-SAME: {{^}}, xiangshan-kunminghu // RISCV64-SAME: {{^}}, xiangshan-nanhu // RISCV64-SAME: {{^}}, xt-c910v2 @@ -129,6 +130,7 @@ // TUNE-RISCV64-SAME: {{^}}, syntacore-scr5-rv64 // TUNE-RISCV64-SAME: {{^}}, syntacore-scr7 // TUNE-RISCV64-SAME: {{^}}, tt-ascalon-x +// TUNE-RISCV64-SAME: {{^}}, tt-ascalon-xg // TUNE-RISCV64-SAME: {{^}}, xiangshan-kunminghu // TUNE-RISCV64-SAME: {{^}}, xiangshan-nanhu // TUNE-RISCV64-SAME: {{^}}, xt-c910v2 diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index 93674c1825367..755952b4cbf9c 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -288,6 +288,9 @@ Makes programs 10x faster by doing Special New Thing. latest specification, placing ``p`` after ``v`` and removing unused ``n``. * Adds experimental assembler support for the `Xqccmi` (Qualcomm 16-bit Instruction Lookup Table) vendor extension. * Added `-mcpu=gaisler-gr765` for the 64-bit GR765 processor. +* Added `-mcpu=tt-ascalon-xg` for the Tenstorrent Ascalon XG processor, the + global variant of Ascalon X without `Zvkng` and with reduced vector FP64 + throughput. ### Changes to the WebAssembly Backend diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index eb4e2214dc389..04a2fabc2c4fe 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -732,38 +732,47 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7", FeatureStdExtZkn], [TuneNoDefaultUnroll, TunePostRAScheduler]>; +defvar TTAscalonXGFeatures = !listconcat(RVA23S64Features, + [FeatureStdExtSmaia, + FeatureStdExtSmmpm, + FeatureStdExtSmnpm, + FeatureStdExtSmrnmi, + FeatureStdExtSmstateen, + FeatureStdExtSsaia, + FeatureStdExtSsstrict, + FeatureStdExtZfbfmin, + FeatureStdExtZfh, + FeatureStdExtZkr, + FeatureStdExtZvbc, + FeatureStdExtZvfbfmin, + FeatureStdExtZvfbfwma, + FeatureStdExtZvfh, + FeatureStdExtZvl256b, + FeatureUnalignedScalarMem, + FeatureUnalignedVectorMem]); + +defvar TTAscalonTuneFeatures = [TuneNoDefaultUnroll, + TuneNLogNVRGather, + TuneOptimizedNF2SegmentLoadStore, + TuneOptimizedNF3SegmentLoadStore, + TuneOptimizedNF4SegmentLoadStore, + TuneOptimizedNF5SegmentLoadStore, + TuneOptimizedNF6SegmentLoadStore, + TuneOptimizedNF7SegmentLoadStore, + TuneOptimizedNF8SegmentLoadStore, + TuneOptimizedZeroStrideLoad, + TunePostRAScheduler]; + def TENSTORRENT_ASCALON_X : RISCVProcessorModel<"tt-ascalon-x", TTAscalonXModel, - !listconcat(RVA23S64Features, - [FeatureStdExtSmaia, - FeatureStdExtSmmpm, - FeatureStdExtSmnpm, - FeatureStdExtSmrnmi, - FeatureStdExtSmstateen, - FeatureStdExtSsaia, - FeatureStdExtSsstrict, - FeatureStdExtZfbfmin, - FeatureStdExtZfh, - FeatureStdExtZkr, - FeatureStdExtZvbc, - FeatureStdExtZvfbfmin, - FeatureStdExtZvfbfwma, - FeatureStdExtZvfh, - FeatureStdExtZvkng, - FeatureStdExtZvl256b, - FeatureUnalignedScalarMem, - FeatureUnalignedVectorMem]), - [TuneNoDefaultUnroll, - TuneNLogNVRGather, - TuneOptimizedNF2SegmentLoadStore, - TuneOptimizedNF3SegmentLoadStore, - TuneOptimizedNF4SegmentLoadStore, - TuneOptimizedNF5SegmentLoadStore, - TuneOptimizedNF6SegmentLoadStore, - TuneOptimizedNF7SegmentLoadStore, - TuneOptimizedNF8SegmentLoadStore, - TuneOptimizedZeroStrideLoad, - TunePostRAScheduler]>; + !listconcat(TTAscalonXGFeatures, + [FeatureStdExtZvkng]), + TTAscalonTuneFeatures>; + +def TENSTORRENT_ASCALON_XG : RISCVProcessorModel<"tt-ascalon-xg", + TTAscalonXGModel, + TTAscalonXGFeatures, + TTAscalonTuneFeatures>; def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu", XiangShanNanHuModel, diff --git a/llvm/lib/Target/RISCV/RISCVSchedTTAscalonX.td b/llvm/lib/Target/RISCV/RISCVSchedTTAscalonX.td index d6a1f341e3e33..0dc6f06079b02 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedTTAscalonX.td +++ b/llvm/lib/Target/RISCV/RISCVSchedTTAscalonX.td @@ -1,4 +1,4 @@ -//=- RISCVSchedTTAscalonX.td - TT Ascalon X Sched Defs -------*- tablegen -*-=// +//=- RISCVSchedTTAscalonX.td - TT Ascalon X/XG Sched Defs ----*- tablegen -*-=// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -95,7 +95,7 @@ class AscalonGetCyclesStridedSegmented<string mx, int sew> { //===----------------------------------------------------------------------===// -def TTAscalonXModel : SchedMachineModel { +class TTAscalonSchedMachineModel : SchedMachineModel { let IssueWidth = 8; // 8-way decode and dispatch let MicroOpBufferSize = 256; // 256 micro-op re-order buffer let LoadLatency = 4; // Optimistic load latency @@ -108,935 +108,1006 @@ def TTAscalonXModel : SchedMachineModel { HasStdExtZcmt, HasStdExtZknd, HasStdExtZkne, HasStdExtZknh, HasStdExtZksed, HasStdExtZksh, HasStdExtZkr]; -} - -let SchedModel = TTAscalonXModel in { -//===----------------------------------------------------------------------===// -// Define each kind of processor resource and number available. - -let BufferSize = 16 in { - def AscalonLS : ProcResource<3>; - def AscalonFXA : ProcResource<1>; // ALU, FP/VEC -> INT, MUL, DIV, CSR - def AscalonFXB : ProcResource<1>; // ALU, INT -> FP/VEC - def AscalonFXC : ProcResource<2>; // ALU, BR - def AscalonFXD : ProcResource<2>; // ALU - def AscalonFX : ProcResGroup<[AscalonFXA, AscalonFXB, AscalonFXC, AscalonFXD]>; - // FP - def AscalonFPA : ProcResource<1>; // Pipe A also handles FP/VEC -> INT - def AscalonFPB : ProcResource<1>; - def AscalonFP : ProcResGroup<[AscalonFPA, AscalonFPB]>; - // Vector - def AscalonVA : ProcResource<1>; - def AscalonVB : ProcResource<1>; - def AscalonV : ProcResGroup<[AscalonVA, AscalonVB]>; + string Name; + bit HasReducedFP64VectorThroughput; } +def TTAscalonXModel : TTAscalonSchedMachineModel { + // TODO: This should technically be AscalonX. + let Name = "Ascalon"; + let HasReducedFP64VectorThroughput = false; +} -//===----------------------------------------------------------------------===// +def TTAscalonXGModel : TTAscalonSchedMachineModel { + let Name = "AscalonXG"; + let HasReducedFP64VectorThroughput = true; +} -// Branching -def : WriteRes<WriteJmp, [AscalonFXC]>; -def : WriteRes<WriteJal, [AscalonFXC]>; -def : WriteRes<WriteJalr, [AscalonFXC]>; - -// Integer arithmetic and logic -def : WriteRes<WriteIALU32, [AscalonFX]>; -def : WriteRes<WriteIALU, [AscalonFX]>; -def : WriteRes<WriteShiftImm32, [AscalonFX]>; -def : WriteRes<WriteShiftImm, [AscalonFX]>; -def : WriteRes<WriteShiftReg32, [AscalonFX]>; -def : WriteRes<WriteShiftReg, [AscalonFX]>; - -// Integer multiplication -let Latency = 3 in { -def : WriteRes<WriteIMul, [AscalonFXA]>; -def : WriteRes<WriteIMul32, [AscalonFXA]>; +/// Latency and occupancy of the extra FP64 vector unit on Ascalon XG for +/// vector instructions producing FP64 results. +class AscalonXGFP64Vec<int Cycles> { + int Latency = !add(Cycles, 8); + int ReleaseAtCycles = !mul(Cycles, 4); } -// Integer division -// Worst case latency is used. +multiclass TTAscalonSchedResources<bit ReducedFP64Vec> { + //===--------------------------------------------------------------------===// + // Define each kind of processor resource and number available. + let BufferSize = 16 in { + def LS : ProcResource<3>; + def FXA : ProcResource<1>; // ALU, FP/VEC -> INT, MUL, DIV, CSR + def FXB : ProcResource<1>; // ALU, INT -> FP/VEC + def FXC : ProcResource<2>; // ALU, BR + def FXD : ProcResource<2>; // ALU + def FX : ProcResGroup<[!cast<ProcResource>(NAME # "FXA"), + !cast<ProcResource>(NAME # "FXB"), + !cast<ProcResource>(NAME # "FXC"), + !cast<ProcResource>(NAME # "FXD")]>; + // FP + def FPA : ProcResource<1>; // Pipe A also handles FP/VEC -> INT + def FPB : ProcResource<1>; + def FP : ProcResGroup<[!cast<ProcResource>(NAME # "FPA"), + !cast<ProcResource>(NAME # "FPB")]>; + // Vector + def VA : ProcResource<1>; + def VB : ProcResource<1>; + def V : ProcResGroup<[!cast<ProcResource>(NAME # "VA"), + !cast<ProcResource>(NAME # "VB")]>; + // Extra unit that models the reduced throughput of vector instructions + // producing FP64 results. + if ReducedFP64Vec then + def FP64V : ProcResource<2>; + } -let Latency = 7, ReleaseAtCycles = [7] in { - def : WriteRes<WriteIDiv32, [AscalonFXA]>; - def : WriteRes<WriteIDiv, [AscalonFXA]>; - def : WriteRes<WriteIRem32, [AscalonFXA]>; - def : WriteRes<WriteIRem, [AscalonFXA]>; -} + defvar AscalonLS = !cast<ProcResource>(NAME # "LS"); + defvar AscalonFXA = !cast<ProcResource>(NAME # "FXA"); + defvar AscalonFXB = !cast<ProcResource>(NAME # "FXB"); + defvar AscalonFXC = !cast<ProcResource>(NAME # "FXC"); + defvar AscalonFXD = !cast<ProcResource>(NAME # "FXD"); + defvar AscalonFX = !cast<ProcResGroup>(NAME # "FX"); + defvar AscalonFPA = !cast<ProcResource>(NAME # "FPA"); + defvar AscalonFPB = !cast<ProcResource>(NAME # "FPB"); + defvar AscalonFP = !cast<ProcResGroup>(NAME # "FP"); + defvar AscalonVA = !cast<ProcResource>(NAME # "VA"); + defvar AscalonVB = !cast<ProcResource>(NAME # "VB"); + defvar AscalonV = !cast<ProcResGroup>(NAME # "V"); + + // Only used when ReducedFP64Vec is set; fall back to the vector pipes + // otherwise so that the defvar is always well-formed. + defvar AscalonFP64V = !if(ReducedFP64Vec, + !cast<ProcResource>(NAME # "FP64V"), AscalonV); + + //===--------------------------------------------------------------------===// + // Branching + def : WriteRes<WriteJmp, [AscalonFXC]>; + def : WriteRes<WriteJal, [AscalonFXC]>; + def : WriteRes<WriteJalr, [AscalonFXC]>; + + // Integer arithmetic and logic + def : WriteRes<WriteIALU32, [AscalonFX]>; + def : WriteRes<WriteIALU, [AscalonFX]>; + def : WriteRes<WriteShiftImm32, [AscalonFX]>; + def : WriteRes<WriteShiftImm, [AscalonFX]>; + def : WriteRes<WriteShiftReg32, [AscalonFX]>; + def : WriteRes<WriteShiftReg, [AscalonFX]>; + + // Integer multiplication + let Latency = 3 in { + def : WriteRes<WriteIMul, [AscalonFXA]>; + def : WriteRes<WriteIMul32, [AscalonFXA]>; + } -// Bitmanip -def : WriteRes<WriteRotateImm, [AscalonFX]>; -def : WriteRes<WriteRotateImm32, [AscalonFX]>; -def : WriteRes<WriteRotateReg, [AscalonFX]>; -def : WriteRes<WriteRotateReg32, [AscalonFX]>; - -def : WriteRes<WriteCLZ, [AscalonFX]>; -def : WriteRes<WriteCLZ32, [AscalonFX]>; -def : WriteRes<WriteCTZ, [AscalonFX]>; -def : WriteRes<WriteCTZ32, [AscalonFX]>; - -def : WriteRes<WriteCPOP, [AscalonFX]>; -def : WriteRes<WriteCPOP32, [AscalonFX]>; - -def : WriteRes<WriteORCB, [AscalonFX]>; - -def : WriteRes<WriteIMinMax, [AscalonFX]>; - -def : WriteRes<WriteREV8, [AscalonFX]>; - -def : WriteRes<WriteSHXADD, [AscalonFX]>; -def : WriteRes<WriteSHXADD32, [AscalonFX]>; - -// Single-bit instructions -def : WriteRes<WriteSingleBit, [AscalonFX]>; -def : WriteRes<WriteSingleBitImm, [AscalonFX]>; -def : WriteRes<WriteBEXT, [AscalonFX]>; -def : WriteRes<WriteBEXTI, [AscalonFX]>; - -// Memory -def : WriteRes<WriteSTB, [AscalonLS]>; -def : WriteRes<WriteSTH, [AscalonLS]>; -def : WriteRes<WriteSTW, [AscalonLS]>; -def : WriteRes<WriteSTD, [AscalonLS]>; -def : WriteRes<WriteFST16, [AscalonLS]>; -def : WriteRes<WriteFST32, [AscalonLS]>; -def : WriteRes<WriteFST64, [AscalonLS]>; - -let Latency = 4 in { -def : WriteRes<WriteLDB, [AscalonLS]>; -def : WriteRes<WriteLDH, [AscalonLS]>; -def : WriteRes<WriteLDW, [AscalonLS]>; -def : WriteRes<WriteLDD, [AscalonLS]>; -def : WriteRes<WriteFLD16, [AscalonLS]>; -def : WriteRes<WriteFLD32, [AscalonLS]>; -def : WriteRes<WriteFLD64, [AscalonLS]>; -} + // Integer division + // Worst case latency is used. -// Atomic memory -def : WriteRes<WriteAtomicSTW, [AscalonLS]>; -def : WriteRes<WriteAtomicSTD, [AscalonLS]>; + let Latency = 7, ReleaseAtCycles = [7] in { + def : WriteRes<WriteIDiv32, [AscalonFXA]>; + def : WriteRes<WriteIDiv, [AscalonFXA]>; + def : WriteRes<WriteIRem32, [AscalonFXA]>; + def : WriteRes<WriteIRem, [AscalonFXA]>; + } -let Latency = 4 in { -def : WriteRes<WriteAtomicW, [AscalonLS]>; -def : WriteRes<WriteAtomicD, [AscalonLS]>; -def : WriteRes<WriteAtomicLDW, [AscalonLS]>; -def : WriteRes<WriteAtomicLDD, [AscalonLS]>; -} + // Bitmanip + def : WriteRes<WriteRotateImm, [AscalonFX]>; + def : WriteRes<WriteRotateImm32, [AscalonFX]>; + def : WriteRes<WriteRotateReg, [AscalonFX]>; + def : WriteRes<WriteRotateReg32, [AscalonFX]>; + + def : WriteRes<WriteCLZ, [AscalonFX]>; + def : WriteRes<WriteCLZ32, [AscalonFX]>; + def : WriteRes<WriteCTZ, [AscalonFX]>; + def : WriteRes<WriteCTZ32, [AscalonFX]>; + + def : WriteRes<WriteCPOP, [AscalonFX]>; + def : WriteRes<WriteCPOP32, [AscalonFX]>; + + def : WriteRes<WriteORCB, [AscalonFX]>; + + def :... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/229030 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
