lenary wrote: > @rjmccall I am going to add commits to this branch that implement the > following: > > 1. Integer args — kept the C convention's 8 registers (a0–a7); no change > needed. > 2. Returns — swiftcall now returns directly in up to 4 registers (a0–a3 / > fa0–fa3) instead of 2, in CC_RISCV_Impl (RISCVCallingConv.cpp). Four matches > clang's SwiftABIInfo::shouldPassIndirectly limit exactly, so frontend and > backend agree; larger returns demote to sret as before.
iirc, clang tracks how many args/returns fit in registers to add `signext` or `zeroext` attributes, so clang changes may be required here. > 3. FP registers — swiftcall follows the selected floating-point ABI: > hard-float ABIs use fa0–fa7 for args / fa0–fa3 for returns; -mabi=lp64 is the > explicit soft-float opt-out. > 4. Context register — swiftself goes in x20 (s4), mirroring AArch64; already > callee-saved, so preservation falls out of normal spilling. x21/x22 are > informally reserved for future swifterror/swiftasync. It's not clear to me why `swiftself` is in x20 on aarch64, when x19 is the first callee-save, but given this oddity, i'm not sure it fundamentally matters which callee-save to use (except to avoid `s0` because that might be used as a frame pointer). `s1` is the only other RVC-compatible s-register, the others all being outside the x8-x15 range, but I think it's probably best to avoid putting the context in an RVC-compatible register so it can be used for something else, so `s4` is fine. > > At this moment I would not yet implement lowering for swifterror/swiftasync. > Would that be acceptable? Sure. https://github.com/llvm/llvm-project/pull/213448 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
