================
@@ -6462,6 +6462,65 @@ static SDValue
lowerVECTOR_SHUFFLEAsPZip(ShuffleVectorSDNode *SVN,
return SDValue();
}
+// Match a strided-interleave shuffle that forms a P-extension packed
+// narrowing zip:
+// <a0, b0, a2, b2, ...> -> ppaire.*
+// <a1, b1, a3, b3, ...> -> ppairo.*
+static SDValue lowerVECTOR_SHUFFLEAsPNarrowingZip(ShuffleVectorSDNode *SVN,
+ SelectionDAG &DAG,
+ bool IsRV64) {
+ MVT VT = SVN->getSimpleValueType(0);
+ if (VT != MVT::v4i8 && VT != MVT::v8i8 && VT != MVT::v4i16)
+ return SDValue();
+
+ SDValue V1 = SVN->getOperand(0);
+ SDValue V2 = SVN->getOperand(1);
+ SDLoc DL(SVN);
+ unsigned NumElts = VT.getVectorNumElements();
+ ArrayRef<int> Mask = SVN->getMask();
+ if (V2.isUndef())
+ return SDValue();
+
+ // Match <start, N+start, start+2, N+start+2, ...>: each widened element of
+ // V1/V2 contributes its low (start=0, ppaire) or high (start=1, ppairo)
byte.
+ // Trailing lanes may be undef when a 4-byte source was widened to v8i8.
+ auto IsStrided = [&](unsigned Start) {
+ for (unsigned I = 0; I != NumElts / 2; ++I) {
+ int M0 = Mask[2 * I];
+ int M1 = Mask[2 * I + 1];
+ if (M0 < 0 && M1 < 0)
+ continue;
+ if (M0 != (int)(Start + 2 * I) || M1 != (int)(NumElts + Start + 2 * I))
+ return false;
+ }
+ return true;
+ };
+
+ bool IsOdd;
+ if (IsStrided(0))
+ IsOdd = false;
+ else if (IsStrided(1))
+ IsOdd = true;
+ else
+ return SDValue();
+
+ unsigned Opc = IsOdd ? RISCVISD::PPAIRO : RISCVISD::PPAIRE;
+
+ // v4i8 is not a legal P-extension type on RV64; zero-extend the operands to
----------------
topperc wrote:
How can VT be v4i8 on RV64? Isn't this code only run after type legalization?
https://github.com/llvm/llvm-project/pull/210040
_______________________________________________
cfe-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
