llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-risc-v Author: TelGome <details> <summary>Changes</summary> This pr support RISC-V P extension intrinsics [Packed Narrowing Zip](https://github.com/riscv/riscv-p-spec/blob/master/P-ext-intrinsics.adoc#packed-narrowing-zip) --- Patch is 31.00 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/210040.diff 6 Files Affected: - (modified) clang/lib/Headers/riscv_packed_simd.h (+43) - (modified) clang/test/CodeGen/RISCV/rvp-intrinsics.c (+266) - (modified) cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c (+80) - (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+62) - (modified) llvm/lib/Target/RISCV/RISCVInstrInfoP.td (+25) - (added) llvm/test/CodeGen/RISCV/rvp-narrowing-zip.ll (+99) ``````````diff diff --git a/clang/lib/Headers/riscv_packed_simd.h b/clang/lib/Headers/riscv_packed_simd.h index 21953fdee1fce..88deb3a77c760 100644 --- a/clang/lib/Headers/riscv_packed_simd.h +++ b/clang/lib/Headers/riscv_packed_simd.h @@ -176,6 +176,29 @@ typedef uint32_t uint32x2_t __attribute__((__vector_size__(8))); return __builtin_shufflevector(__rs1, __rs1, 1, 3, 5, 7); \ } +#define __packed_nzip2(name, rty, ty) \ + static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, \ + ty __rs2) { \ + return __builtin_shufflevector((rty)__rs1, (rty)__rs2, 0, 4, 2, 6); \ + } +#define __packed_nzip4(name, rty, ty) \ + static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, \ + ty __rs2) { \ + return __builtin_shufflevector((rty)__rs1, (rty)__rs2, 0, 8, 2, 10, 4, 12, \ + 6, 14); \ + } +#define __packed_nziph2(name, rty, ty) \ + static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, \ + ty __rs2) { \ + return __builtin_shufflevector((rty)__rs1, (rty)__rs2, 1, 5, 3, 7); \ + } +#define __packed_nziph4(name, rty, ty) \ + static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, \ + ty __rs2) { \ + return __builtin_shufflevector((rty)__rs1, (rty)__rs2, 1, 9, 3, 11, 5, 13, \ + 7, 15); \ + } + #define __packed_abdsum(name, rty, ty, builtin) \ static __inline__ rty __DEFAULT_FN_ATTRS __riscv_##name(ty __rs1, \ ty __rs2) { \ @@ -509,6 +532,22 @@ __packed_unzipo2(punzipo_i16x2, int16x2_t, int16x4_t) __packed_unzipe2(punzipe_u16x2, uint16x2_t, uint16x4_t) __packed_unzipo2(punzipo_u16x2, uint16x2_t, uint16x4_t) +/* Packed Narrowing Zip (32-bit) */ +__packed_nzip2(pnzip_i8x4, int8x4_t, int16x2_t) +__packed_nzip2(pnzip_u8x4, uint8x4_t, uint16x2_t) +__packed_nziph2(pnziph_i8x4, int8x4_t, int16x2_t) +__packed_nziph2(pnziph_u8x4, uint8x4_t, uint16x2_t) + +/* Packed Narrowing Zip (64-bit) */ +__packed_nzip4(pnzip_i8x8, int8x8_t, int16x4_t) +__packed_nzip4(pnzip_u8x8, uint8x8_t, uint16x4_t) +__packed_nzip2(pnzip_i16x4, int16x4_t, int32x2_t) +__packed_nzip2(pnzip_u16x4, uint16x4_t, uint32x2_t) +__packed_nziph4(pnziph_i8x8, int8x8_t, int16x4_t) +__packed_nziph4(pnziph_u8x8, uint8x8_t, uint16x4_t) +__packed_nziph2(pnziph_i16x4, int16x4_t, int32x2_t) +__packed_nziph2(pnziph_u16x4, uint16x4_t, uint32x2_t) + /* Packed Averaging Addition and Subtraction (32-bit) */ __packed_binary_builtin(paadd_i8x4, int8x4_t, __builtin_riscv_paadd_i8x4) __packed_binary_builtin(paadd_i16x2, int16x2_t, __builtin_riscv_paadd_i16x2) @@ -633,6 +672,10 @@ __packed_psabs(psabs_i16x4, int16x4_t, __builtin_riscv_psabs_i16x4) #undef __packed_unzipe4 #undef __packed_unzipo2 #undef __packed_unzipo4 +#undef __packed_nzip2 +#undef __packed_nzip4 +#undef __packed_nziph2 +#undef __packed_nziph4 #undef __packed_abdsum #undef __packed_abdsum_acc #undef __DEFAULT_FN_ATTRS diff --git a/clang/test/CodeGen/RISCV/rvp-intrinsics.c b/clang/test/CodeGen/RISCV/rvp-intrinsics.c index 2244cc816913d..8e48df498be74 100644 --- a/clang/test/CodeGen/RISCV/rvp-intrinsics.c +++ b/clang/test/CodeGen/RISCV/rvp-intrinsics.c @@ -7193,3 +7193,269 @@ int32x2_t test_pwcvth_i32x2(int16x2_t rs1) { uint32x2_t test_pwcvth_u32x2(uint16x2_t rs1) { return __riscv_pwcvth_u32x2(rs1); } + +/* Packed Narrowing Zip */ + +// RV32-LABEL: define dso_local i32 @test_pnzip_i8x4( +// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8> +// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8> +// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6> +// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32 +// RV32-NEXT: ret i32 [[TMP2]] +// +// RV64-LABEL: define dso_local i32 @test_pnzip_i8x4( +// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8> +// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8> +// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6> +// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32 +// RV64-NEXT: ret i32 [[TMP2]] +// +int8x4_t test_pnzip_i8x4(int16x2_t rs1, int16x2_t rs2) { + return __riscv_pnzip_i8x4(rs1, rs2); +} + +// RV32-LABEL: define dso_local i32 @test_pnzip_u8x4( +// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8> +// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8> +// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6> +// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32 +// RV32-NEXT: ret i32 [[TMP2]] +// +// RV64-LABEL: define dso_local i32 @test_pnzip_u8x4( +// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8> +// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8> +// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6> +// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32 +// RV64-NEXT: ret i32 [[TMP2]] +// +uint8x4_t test_pnzip_u8x4(uint16x2_t rs1, uint16x2_t rs2) { + return __riscv_pnzip_u8x4(rs1, rs2); +} + +// RV32-LABEL: define dso_local i32 @test_pnziph_i8x4( +// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8> +// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8> +// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7> +// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32 +// RV32-NEXT: ret i32 [[TMP2]] +// +// RV64-LABEL: define dso_local i32 @test_pnziph_i8x4( +// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8> +// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8> +// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7> +// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32 +// RV64-NEXT: ret i32 [[TMP2]] +// +int8x4_t test_pnziph_i8x4(int16x2_t rs1, int16x2_t rs2) { + return __riscv_pnziph_i8x4(rs1, rs2); +} + +// RV32-LABEL: define dso_local i32 @test_pnziph_u8x4( +// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8> +// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8> +// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7> +// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32 +// RV32-NEXT: ret i32 [[TMP2]] +// +// RV64-LABEL: define dso_local i32 @test_pnziph_u8x4( +// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <4 x i8> +// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <4 x i8> +// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7> +// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i8> [[SHUFFLE_I]] to i32 +// RV64-NEXT: ret i32 [[TMP2]] +// +uint8x4_t test_pnziph_u8x4(uint16x2_t rs1, uint16x2_t rs2) { + return __riscv_pnziph_u8x4(rs1, rs2); +} + +// RV32-LABEL: define dso_local i64 @test_pnzip_i8x8( +// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8> +// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8> +// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14> +// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64 +// RV32-NEXT: ret i64 [[TMP2]] +// +// RV64-LABEL: define dso_local i64 @test_pnzip_i8x8( +// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8> +// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8> +// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14> +// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64 +// RV64-NEXT: ret i64 [[TMP2]] +// +int8x8_t test_pnzip_i8x8(int16x4_t rs1, int16x4_t rs2) { + return __riscv_pnzip_i8x8(rs1, rs2); +} + +// RV32-LABEL: define dso_local i64 @test_pnzip_u8x8( +// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8> +// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8> +// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14> +// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64 +// RV32-NEXT: ret i64 [[TMP2]] +// +// RV64-LABEL: define dso_local i64 @test_pnzip_u8x8( +// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8> +// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8> +// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14> +// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64 +// RV64-NEXT: ret i64 [[TMP2]] +// +uint8x8_t test_pnzip_u8x8(uint16x4_t rs1, uint16x4_t rs2) { + return __riscv_pnzip_u8x8(rs1, rs2); +} + +// RV32-LABEL: define dso_local i64 @test_pnzip_i16x4( +// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16> +// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16> +// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6> +// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64 +// RV32-NEXT: ret i64 [[TMP2]] +// +// RV64-LABEL: define dso_local i64 @test_pnzip_i16x4( +// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16> +// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16> +// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6> +// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64 +// RV64-NEXT: ret i64 [[TMP2]] +// +int16x4_t test_pnzip_i16x4(int32x2_t rs1, int32x2_t rs2) { + return __riscv_pnzip_i16x4(rs1, rs2); +} + +// RV32-LABEL: define dso_local i64 @test_pnzip_u16x4( +// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16> +// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16> +// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6> +// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64 +// RV32-NEXT: ret i64 [[TMP2]] +// +// RV64-LABEL: define dso_local i64 @test_pnzip_u16x4( +// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16> +// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16> +// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 6> +// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64 +// RV64-NEXT: ret i64 [[TMP2]] +// +uint16x4_t test_pnzip_u16x4(uint32x2_t rs1, uint32x2_t rs2) { + return __riscv_pnzip_u16x4(rs1, rs2); +} + +// RV32-LABEL: define dso_local i64 @test_pnziph_i8x8( +// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8> +// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8> +// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15> +// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64 +// RV32-NEXT: ret i64 [[TMP2]] +// +// RV64-LABEL: define dso_local i64 @test_pnziph_i8x8( +// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8> +// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8> +// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15> +// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64 +// RV64-NEXT: ret i64 [[TMP2]] +// +int8x8_t test_pnziph_i8x8(int16x4_t rs1, int16x4_t rs2) { + return __riscv_pnziph_i8x8(rs1, rs2); +} + +// RV32-LABEL: define dso_local i64 @test_pnziph_u8x8( +// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8> +// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8> +// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15> +// RV32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64 +// RV32-NEXT: ret i64 [[TMP2]] +// +// RV64-LABEL: define dso_local i64 @test_pnziph_u8x8( +// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <8 x i8> +// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <8 x i8> +// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[TMP0]], <8 x i8> [[TMP1]], <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15> +// RV64-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[SHUFFLE_I]] to i64 +// RV64-NEXT: ret i64 [[TMP2]] +// +uint8x8_t test_pnziph_u8x8(uint16x4_t rs1, uint16x4_t rs2) { + return __riscv_pnziph_u8x8(rs1, rs2); +} + +// RV32-LABEL: define dso_local i64 @test_pnziph_i16x4( +// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16> +// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16> +// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7> +// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64 +// RV32-NEXT: ret i64 [[TMP2]] +// +// RV64-LABEL: define dso_local i64 @test_pnziph_i16x4( +// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16> +// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16> +// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7> +// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64 +// RV64-NEXT: ret i64 [[TMP2]] +// +int16x4_t test_pnziph_i16x4(int32x2_t rs1, int32x2_t rs2) { + return __riscv_pnziph_i16x4(rs1, rs2); +} + +// RV32-LABEL: define dso_local i64 @test_pnziph_u16x4( +// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16> +// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16> +// RV32-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7> +// RV32-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64 +// RV32-NEXT: ret i64 [[TMP2]] +// +// RV64-LABEL: define dso_local i64 @test_pnziph_u16x4( +// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16> +// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16> +// RV64-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> [[TMP1]], <4 x i32> <i32 1, i32 5, i32 3, i32 7> +// RV64-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to i64 +// RV64-NEXT: ret i64 [[TMP2]] +// +uint16x4_t test_pnziph_u16x4(uint32x2_t rs1, uint32x2_t rs2) { + return __riscv_pnziph_u16x4(rs1, rs2); +} diff --git a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c index a73c0376db9d1..c39c94014fd13 100644 --- a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c +++ b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c @@ -2452,3 +2452,83 @@ int8x8_t test_psabs_i8x8(int8x8_t a) { return __riscv_psabs_i8x8(a); } // RV32: psabs.dh // RV64: psabs.h int16x4_t test_psabs_i16x4(int16x4_t a) { return __riscv_psabs_i16x4(a); } + +// CHECK-LABEL: test_pnzip_i8x4: +// CHECK: ppaire.b +int8x4_t test_pnzip_i8x4(int16x2_t rs1, int16x2_t rs2) { + return __riscv_pnzip_i8x4(rs1, rs2); +} + +// CHECK-LABEL: test_pnzip_u8x4: +// CHECK: ppaire.b +uint8x4_t test_pnzip_u8x4(uint16x2_t rs1, uint16x2_t rs2) { + return __riscv_pnzip_u8x4(rs1, rs2); +} + +// CHECK-LABEL: test_pnziph_i8x4: +// CHECK: ppairo.b +int8x4_t test_pnziph_i8x4(int16x2_t rs1, int16x2_t rs2) { + return __riscv_pnziph_i8x4(rs1, rs2); +} + +// CHECK-LABEL: test_pnziph_u8x4: +// CHECK: ppairo.b +uint8x4_t test_pnziph_u8x4(uint16x2_t rs1, uint16x2_t rs2) { + return __riscv_pnziph_u8x4(rs1, rs2); +} + +// CHECK-LABEL: test_pnzip_i8x8: +// RV32: ppaire.db +// RV64: ppaire.b +int8x8_t test_pnzip_i8x8(int16x4_t rs1, int16x4_t rs2) { + return __riscv_pnzip_i8x8(rs1, rs2); +} + +// CHECK-LABEL: test_pnzip_u8x8: +// RV32: ppai... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/210040 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
