================
@@ -0,0 +1,311 @@
+// REQUIRES: aarch64-registered-target || arm-registered-target
+
+// RUN: %clang_cc1 -triple arm64-none-linux-gnu
-target-feature +neon -disable-O0-optnone -flax-vector-conversions=none
-emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s
--check-prefixes=ALL,LLVM
+// RUN: %if cir-enabled %{%clang_cc1 -triple arm64-none-linux-gnu
-target-feature +neon -disable-O0-optnone -flax-vector-conversions=none
-fclangir -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s
--check-prefixes=ALL,LLVM %}
+// RUN: %if cir-enabled %{%clang_cc1 -triple arm64-none-linux-gnu
-target-feature +neon -disable-O0-optnone -flax-vector-conversions=none
-fclangir -emit-cir -o - %s | FileCheck %s
--check-prefixes=ALL,CIR %}
+
+//=============================================================================
+// NOTES
+//
+// This file contains tests that were originally located in
+// * clang/test/CodeGen/AArch64/neon-vget.c
+// * clang/test/CodeGen/AArch64/poly64.c
+// The main difference is the use of RUN lines that enable ClangIR lowering;
+// therefore only builtins currently supported by ClangIR are tested here.
+//=============================================================================
+
+#include <arm_neon.h>
+
+//===------------------------------------------------------===//
+// Extract one element from vector
+//===------------------------------------------------------===//
+
+// ALL-LABEL: @test_vget_lane_u8(
+uint8_t test_vget_lane_u8(uint8x8_t a) {
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : {{.*}}] : !cir.vector<8 x !u8i>
+
+// LLVM: [[VGET_LANE:%.*]] = extractelement <8 x i8> %{{.*}}, i32 7
----------------
banach-space wrote:
Could you also check the input arguments? Similar suggestion for the other
tests. Thanks!
```suggestion
// LLVM-SAME: <8 x i8> {{.*}} [[A:%.*]])
// LLVM: [[VGET_LANE:%.*]] = extractelement <8 x i8> [[A]], i32 7
```
https://github.com/llvm/llvm-project/pull/186119
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