================
@@ -1399,8 +1400,10 @@ mlir::LogicalResult
CIRToLLVMShiftOpLowering::matchAndRewrite(
if (op.getIsShiftleft()) {
rewriter.replaceOpWithNewOp<mlir::LLVM::ShlOp>(op, llvmTy, val, amt);
} else {
- assert(!cir::MissingFeatures::vectorType());
- bool isUnsigned = !cirValTy.isSigned();
+ const bool isUnsigned =
+ cirValTy
+ ? !cirValTy.isSigned()
+ : !mlir::cast<cir::IntType>(cirValVTy.getElementType()).isSigned();
----------------
AmrDeveloper wrote:
I think we can also simplify the asserts, for example
```
assert((cirValTy == op.getType() || cirValVTy == op.getType()) &&
"inconsistent operands' types NYI");
```
to this, so we check that the value type equals to `op.type`
```
assert((op.getValue().getType() == op.getType()) &&
"inconsistent operands' types NYI");
```
and
```
assert(((cirValTy && cirAmtTy) || (cirAmtVTy && cirValVTy)) &&
"shift input type must be integer or vector type, otherwise NYI");
```
To just check that both are true or false, so both are ints or vectors 🤔
```
assert((cirValTy == cirAmtTy) &&
"shift input type must be integer or vector type, otherwise NYI");
```
https://github.com/llvm/llvm-project/pull/139465
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