================ @@ -1399,8 +1400,10 @@ mlir::LogicalResult CIRToLLVMShiftOpLowering::matchAndRewrite( if (op.getIsShiftleft()) { rewriter.replaceOpWithNewOp<mlir::LLVM::ShlOp>(op, llvmTy, val, amt); } else { - assert(!cir::MissingFeatures::vectorType()); - bool isUnsigned = !cirValTy.isSigned(); + const bool isUnsigned = + cirValTy + ? !cirValTy.isSigned() + : !mlir::cast<cir::IntType>(cirValVTy.getElementType()).isSigned(); ---------------- AmrDeveloper wrote:
Mmmmm, not sure if we should support isSinged() for Vector because it can be a vector of bool, floats ..etc and also we will need to cast again to get width from Vec<Int> here ```cpp if (cirAmtTy) amt = getLLVMIntCast(rewriter, amt, mlir::cast<mlir::IntegerType>(llvmTy), true, cirAmtTy.getWidth(), cirValTy.getWidth()); ``` I will try first to change the code and add bool isAmtVecTy and see if it will become better :D https://github.com/llvm/llvm-project/pull/139465 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits