[clang] [llvm] [RISCV] Add Qualcomm uC Xqcisim (Simulation Hint) extension (PR #128833)

[Craig Topper via cfe-commits]

================
@@ -485,6 +498,43 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
 } // hasSideEffects = 0, mayLoad = 0, mayStore = 0
 } // Predicates = [HasVendorXqcilia, IsRV32]
 
+let Predicates = [HasVendorXqcisim, IsRV32] in {
+let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in {
+  def QC_PSYSCALLI : RVInstI<0b010, OPC_OP_IMM, (outs),
+                                  (ins uimm10:$imm10), "qc.psyscalli",
----------------
topperc wrote:

too much indentation

https://github.com/llvm/llvm-project/pull/128833
_______________________________________________
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits