================
@@ -485,6 +498,43 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
} // Predicates = [HasVendorXqcilia, IsRV32]
+let Predicates = [HasVendorXqcisim, IsRV32] in {
+let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in {
+ def QC_PSYSCALLI : RVInstI<0b010, OPC_OP_IMM, (outs),
+ (ins uimm10:$imm10), "qc.psyscalli",
+ "$imm10"> {
+ bits<10> imm10;
+
+ let rs1 = 0;
+ let rd = 0;
+ let imm12 = {0b00, imm10};
+ }
+
+ def QC_PPUTCI : RVInstI<0b010, OPC_OP_IMM, (outs), (ins uimm8:$imm8),
+ "qc.pputci", "$imm8"> {
+ bits<8> imm8;
+
+ let rs1 = 0;
+ let rd = 0;
+ let imm12 = {0b0100, imm8};
+ }
+
+ def QC_PCOREDUMP : QCISim_NONE<0b0110, "qc.pcoredump">;
+ def QC_PPREGS : QCISim_NONE<0b0111, "qc.ppregs">;
+ def QC_PPREG : QCISim_RS1<0b1000, "qc.ppreg">;
+ def QC_PPUTC : QCISim_RS1<0b1001, "qc.pputc">;
+ def QC_PPUTS : QCISim_RS1<0b1010, "qc.pputs">;
+ def QC_PEXIT : QCISim_RS1<0b1011, "qc.pexit">;
+ def QC_PSYSCALL : QCISim_RS1<0b1100, "qc.psyscall">;
+
+ def QC_C_PTRACE : RVInst16CI<0b000, 0b10, (outs), (ins), "qc.c.ptrace", ""> {
+ let rd = 0;
+ let imm = 0;
+ let Inst{6-2} = 0;
----------------
topperc wrote:
This `Inst{6-2}` line isn't needed. `Inst{6-2}` defaults to `imm{4-0}`. That
change was made in 6829f30883fa7e71e3b7af022916003a82f0216d so it may have been
necessary when this was written in your downstream.
https://github.com/llvm/llvm-project/pull/128833
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