================
@@ -257,6 +257,146 @@ def simm12 : RISCVSImmLeafOp<12> {
}];
}
+// A 7-bit unsigned immediate where the least significant two bits are zero.
----------------
topperc wrote:Why do these need to move? RISCVInstrInfoXMips.td is included after RISCVInstrInfoC.td https://github.com/llvm/llvm-project/pull/121394 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
