llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-clang Author: Djordje Todorovic (djtodoro) <details> <summary>Changes</summary> Adding two extensions for MIPS p8700 CPU: 1. cmove (conditional move) 2. lsp (load/store pair) The official product page here: https://mips.com/products/hardware/p8700 --- Patch is 75.96 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/121394.diff 27 Files Affected: - (modified) clang/include/clang/Driver/Options.td (+4) - (modified) clang/lib/Driver/ToolChains/Clang.cpp (+15) - (modified) llvm/docs/RISCVUsage.rst (+6) - (modified) llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp (+10) - (modified) llvm/lib/Target/RISCV/CMakeLists.txt (+1) - (modified) llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h (+1) - (modified) llvm/lib/Target/RISCV/RISCV.h (+2) - (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+13) - (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+3-1) - (modified) llvm/lib/Target/RISCV/RISCVInstrFormats.td (+72) - (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.cpp (+43) - (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.h (+6) - (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.td (+145) - (modified) llvm/lib/Target/RISCV/RISCVInstrInfoC.td (-125) - (added) llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td (+82) - (added) llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp (+370) - (modified) llvm/lib/Target/RISCV/RISCVProcessors.td (+3-1) - (modified) llvm/lib/Target/RISCV/RISCVSubtarget.cpp (+18) - (modified) llvm/lib/Target/RISCV/RISCVSubtarget.h (+2) - (modified) llvm/lib/Target/RISCV/RISCVTargetMachine.cpp (+15) - (modified) llvm/test/CodeGen/RISCV/O0-pipeline.ll (+1) - (modified) llvm/test/CodeGen/RISCV/O3-pipeline.ll (+2) - (added) llvm/test/CodeGen/RISCV/load-store-pair.ll (+509) - (modified) llvm/test/CodeGen/RISCV/select-and.ll (+25) - (modified) llvm/test/CodeGen/RISCV/select-bare.ll (+14) - (modified) llvm/test/CodeGen/RISCV/select-cc.ll (+86) - (modified) llvm/test/CodeGen/RISCV/select-or.ll (+25) ``````````diff diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index d922709db17786..28b7d70f77d4a2 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -4963,6 +4963,10 @@ def msave_restore : Flag<["-"], "msave-restore">, Group<m_riscv_Features_Group>, def mno_save_restore : Flag<["-"], "mno-save-restore">, Group<m_riscv_Features_Group>, HelpText<"Disable using library calls for save and restore">; } // let Flags = [TargetSpecific] +def mload_store_pairs : Flag<["-"], "mload-store-pairs">, Group<m_riscv_Features_Group>; +def mno_load_store_pairs : Flag<["-"], "mno-load-store-pairs">, Group<m_riscv_Features_Group>; +def mccmov : Flag<["-"], "mccmov">, Group<m_riscv_Features_Group>; +def mno_ccmov : Flag<["-"], "mno-ccmov">, Group<m_riscv_Features_Group>; let Flags = [TargetSpecific] in { def menable_experimental_extensions : Flag<["-"], "menable-experimental-extensions">, Group<m_Group>, HelpText<"Enable use of experimental RISC-V extensions.">; diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp index a020e00cd17392..e91df8838032cd 100644 --- a/clang/lib/Driver/ToolChains/Clang.cpp +++ b/clang/lib/Driver/ToolChains/Clang.cpp @@ -2167,6 +2167,21 @@ void Clang::AddRISCVTargetArgs(const ArgList &Args, CmdArgs.push_back(A->getValue()); } + if (Arg *A = Args.getLastArg(options::OPT_mload_store_pairs, + options::OPT_mno_load_store_pairs)) { + if (A->getOption().matches(options::OPT_mload_store_pairs)) { + CmdArgs.push_back("-mllvm"); + CmdArgs.push_back("-riscv-load-store-pairs=1"); + } + } + + if (Arg *A = Args.getLastArg(options::OPT_mccmov, + options::OPT_mno_ccmov)) { + if (A->getOption().matches(options::OPT_mno_ccmov)) { + CmdArgs.push_back("-mllvm"); + CmdArgs.push_back("-riscv-ccmov=0"); + } + } // Handle -mrvv-vector-bits=<bits> if (Arg *A = Args.getLastArg(options::OPT_mrvv_vector_bits_EQ)) { StringRef Val = A->getValue(); diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 22600f5720553e..06b32a69cef9ea 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -444,6 +444,12 @@ The current vendor extensions supported are: ``experimental-Xqcisls`` LLVM implements `version 0.2 of the Qualcomm uC Scaled Load Store extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32. +``Xmipscmove`` + LLVM implements conditional move for the `p8700 processor <https://mips.com/products/hardware/p8700/>` by MIPS. + +``Xmipslsp`` + LLVM implements load/store pair instructions for the `p8700 processor <https://mips.com/products/hardware/p8700/>` by MIPS. + Experimental C Intrinsics ========================= diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp index 4c1fd5aa41e2b7..76eb5254a19a34 100644 --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -876,6 +876,16 @@ struct RISCVOperand final : public MCParsedAsmOperand { VK == RISCVMCExpr::VK_RISCV_None; } + bool isUImm7Lsb000() const { + if (!isImm()) + return false; + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); + return IsConstantImm && isShiftedUInt<4, 3>(Imm) && + VK == RISCVMCExpr::VK_RISCV_None; + } + bool isUImm8Lsb00() const { if (!isImm()) return false; diff --git a/llvm/lib/Target/RISCV/CMakeLists.txt b/llvm/lib/Target/RISCV/CMakeLists.txt index 44661647a86310..cc9bf5727cbdf5 100644 --- a/llvm/lib/Target/RISCV/CMakeLists.txt +++ b/llvm/lib/Target/RISCV/CMakeLists.txt @@ -47,6 +47,7 @@ add_llvm_target(RISCVCodeGen RISCVISelLowering.cpp RISCVLandingPadSetup.cpp RISCVMachineFunctionInfo.cpp + RISCVLoadStoreOptimizer.cpp RISCVMergeBaseOffset.cpp RISCVOptWInstrs.cpp RISCVPostRAExpandPseudoInsts.cpp diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h index 7fb5fc7a831308..f51a9205cbd460 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h @@ -308,6 +308,7 @@ enum OperandType : unsigned { OPERAND_UIMM6_LSB0, OPERAND_UIMM7, OPERAND_UIMM7_LSB00, + OPERAND_UIMM7_LSB000, OPERAND_UIMM8_LSB00, OPERAND_UIMM8, OPERAND_UIMM8_LSB000, diff --git a/llvm/lib/Target/RISCV/RISCV.h b/llvm/lib/Target/RISCV/RISCV.h index d7bab601d545cc..b1aee98739e852 100644 --- a/llvm/lib/Target/RISCV/RISCV.h +++ b/llvm/lib/Target/RISCV/RISCV.h @@ -84,6 +84,8 @@ void initializeRISCVMoveMergePass(PassRegistry &); FunctionPass *createRISCVPushPopOptimizationPass(); void initializeRISCVPushPopOptPass(PassRegistry &); +FunctionPass *createRISCVLoadStoreOptPass(); +void initializeRISCVLoadStoreOptPass(PassRegistry &); FunctionPass *createRISCVZacasABIFixPass(); void initializeRISCVZacasABIFixPass(PassRegistry &); diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 916b140c5bde75..9ba2c92cc90d1a 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1395,6 +1395,19 @@ def NoConditionalMoveFusion : Predicate<"!Subtarget->hasConditionalMoveFusion() def TuneMIPSP8700 : SubtargetFeature<"mips-p8700", "RISCVProcFamily", "MIPSP8700", "MIPS p8700 processor">; +def FeatureVendorMIPSCMove : SubtargetFeature<"xmipscmove", "HasVendorMIPSCMove", + "true", "Using CCMov", + [Feature64Bit]>; +def HasVendorMIPSCMove + : Predicate<"Subtarget->useCCMovInsn()">, + AssemblerPredicate<(all_of FeatureVendorMIPSCMove), "'ccmov' instruction">; +def FeatureVendorMIPSLoadStorePairs + : SubtargetFeature<"xmipslsp", "HasMIPSLSP", "true", + "Optimize for hardware load-store bonding">; +def HasVendorMIPSLoadStorePairs + : Predicate<"Subtarget->useLoadStorePairs()">, + AssemblerPredicate<(all_of FeatureVendorMIPSLoadStorePairs), + "load and store pair instructions">; def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7", "SiFive 7-Series processors">; diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index cda64ae5f498d3..88dd9f0ec4f18c 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -409,7 +409,9 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, setOperationAction(ISD::ABS, MVT::i32, Custom); } - if (!Subtarget.hasVendorXTHeadCondMov()) + if (Subtarget.hasVendorMIPSCMove()) + setOperationAction(ISD::SELECT, XLenVT, Legal); + else if (!Subtarget.hasVendorXTHeadCondMov()) setOperationAction(ISD::SELECT, XLenVT, Custom); static const unsigned FPLegalNodeTypes[] = { diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td index 013c26c72bfd55..9ffed2c80ad6d3 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td +++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td @@ -514,6 +514,78 @@ class RVInstJ<RISCVOpcode opcode, dag outs, dag ins, string opcodestr, let Inst{6-0} = opcode.Value; } +//===----------------------------------------------------------------------===// +// MIPS custom instruction formats +//===----------------------------------------------------------------------===// + +// Load double pair format. +class LDPFormat<dag outs, dag ins, string opcodestr, string argstr> + : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> { + bits<7> imm7; + bits<5> rs1; + bits<5> rd1; + bits<5> rd2; + + let Inst{31-27} = rd2; + let Inst{26-23} = imm7{6-3}; + let Inst{22-20} = 0b000; + let Inst{19-15} = rs1; + let Inst{14-12} = 0b100; + let Inst{11-7} = rd1; + let Inst{6-0} = 0b0001011; +} + +// Load word pair format. +class LWPFormat<dag outs, dag ins, string opcodestr, string argstr> + : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> { + bits<7> imm7; + bits<5> rs1; + bits<5> rd1; + bits<5> rd2; + + let Inst{31-27} = rd2; + let Inst{26-22} = imm7{6-2}; + let Inst{21-20} = 0b01; + let Inst{19-15} = rs1; + let Inst{14-12} = 0b100; + let Inst{11-7} = rd1; + let Inst{6-0} = 0b0001011; +} + +// Store double pair format. +class SDPFormat<dag outs, dag ins, string opcodestr, string argstr> + : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> { + bits<7> imm7; + bits<5> rs3; + bits<5> rs2; + bits<5> rs1; + + let Inst{31-27} = rs3; + let Inst{26-25} = imm7{6-5}; + let Inst{24-20} = rs2; + let Inst{19-15} = rs1; + let Inst{14-12} = 0b101; + let Inst{11-10} = imm7{4-3}; + let Inst{9-0} = 0b0000001011; +} + +// Store word pair format. +class SWPFormat<dag outs, dag ins, string opcodestr, string argstr> + : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> { + bits<7> imm7; + bits<5> rs3; + bits<5> rs2; + bits<5> rs1; + + let Inst{31-27} = rs3; + let Inst{26-25} = imm7{6-5}; + let Inst{24-20} = rs2; + let Inst{19-15} = rs1; + let Inst{14-12} = 0b101; + let Inst{11-9} = imm7{4-2}; + let Inst{8-0} = 0b010001011; +} + //===----------------------------------------------------------------------===// // Instruction classes for .insn directives //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index f24940795e433f..c92c8e8077c7a3 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -2488,6 +2488,9 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI, case RISCVOp::OPERAND_UIMM7_LSB00: Ok = isShiftedUInt<5, 2>(Imm); break; + case RISCVOp::OPERAND_UIMM7_LSB000: + Ok = isShiftedUInt<4, 3>(Imm); + break; case RISCVOp::OPERAND_UIMM8_LSB00: Ok = isShiftedUInt<6, 2>(Imm); break; @@ -2734,6 +2737,46 @@ MachineInstr *RISCVInstrInfo::emitLdStWithAddr(MachineInstr &MemI, .setMIFlags(MemI.getFlags()); } +bool RISCVInstrInfo::isPairableLdStInstOpc(unsigned Opc) { + switch (Opc) { + default: + return false; + case RISCV::SH: + case RISCV::LH: + case RISCV::LHU: + case RISCV::SW: + case RISCV::FSW: + case RISCV::LW: + case RISCV::FLW: + case RISCV::SD: + case RISCV::FSD: + case RISCV::LD: + case RISCV::FLD: + return true; + } +} + +bool RISCVInstrInfo::isLdStSafeToPair(const MachineInstr &LdSt, + const TargetRegisterInfo *TRI) { + // If this is a volatile load/store, don't mess with it. + if (LdSt.hasOrderedMemoryRef() || LdSt.getNumExplicitOperands() != 3) + return false; + + if (LdSt.getOperand(1).isFI()) + return true; + + assert(LdSt.getOperand(1).isReg() && "Expected a reg operand."); + // Can't cluster if the instruction modifies the base register + // or it is update form. e.g. ld x5,8(x5) + if (LdSt.modifiesRegister(LdSt.getOperand(1).getReg(), TRI)) + return false; + + if (!LdSt.getOperand(2).isImm()) + return false; + + return true; +} + bool RISCVInstrInfo::getMemOperandsWithOffsetWidth( const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width, diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h index 7e8bcd451a8ef8..ef81c2d4397f26 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h @@ -301,6 +301,12 @@ class RISCVInstrInfo : public RISCVGenInstrInfo { std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo> analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override; + /// Return true if pairing the given load or store may be paired with another. + static bool isPairableLdStInstOpc(unsigned Opc); + + static bool isLdStSafeToPair(const MachineInstr &LdSt, + const TargetRegisterInfo *TRI); + protected: const RISCVSubtarget &STI; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index 1260f99ad9dcd0..3e29e77aa3db6f 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -257,6 +257,146 @@ def simm12 : RISCVSImmLeafOp<12> { }]; } +// A 7-bit unsigned immediate where the least significant two bits are zero. +def uimm7_lsb00 : RISCVOp, + ImmLeaf<XLenVT, [{return isShiftedUInt<5, 2>(Imm);}]> { + let ParserMatchClass = UImmAsmOperand<7, "Lsb00">; + let EncoderMethod = "getImmOpValue"; + let DecoderMethod = "decodeUImmOperand<7>"; + let OperandType = "OPERAND_UIMM7_LSB00"; + let MCOperandPredicate = [{ + int64_t Imm; + if (!MCOp.evaluateAsConstantImm(Imm)) + return false; + return isShiftedUInt<5, 2>(Imm); + }]; +} + +// A 7-bit unsigned immediate where the least significant three bits are zero. +def uimm7_lsb000 : RISCVOp, + ImmLeaf<XLenVT, [{return isShiftedUInt<4, 3>(Imm);}]> { + let ParserMatchClass = UImmAsmOperand<7, "Lsb000">; + let EncoderMethod = "getImmOpValue"; + let DecoderMethod = "decodeUImmOperand<7>"; + let OperandType = "OPERAND_UIMM7_LSB000"; + let MCOperandPredicate = [{ + int64_t Imm; + if (!MCOp.evaluateAsConstantImm(Imm)) + return false; + return isShiftedUInt<4, 3>(Imm); + }]; +} + +// A 8-bit unsigned immediate where the least significant two bits are zero. +def uimm8_lsb00 : RISCVOp, + ImmLeaf<XLenVT, [{return isShiftedUInt<6, 2>(Imm);}]> { + let ParserMatchClass = UImmAsmOperand<8, "Lsb00">; + let EncoderMethod = "getImmOpValue"; + let DecoderMethod = "decodeUImmOperand<8>"; + let OperandType = "OPERAND_UIMM8_LSB00"; + let MCOperandPredicate = [{ + int64_t Imm; + if (!MCOp.evaluateAsConstantImm(Imm)) + return false; + return isShiftedUInt<6, 2>(Imm); + }]; +} + +// A 8-bit unsigned immediate where the least significant three bits are zero. +def uimm8_lsb000 : RISCVOp, + ImmLeaf<XLenVT, [{return isShiftedUInt<5, 3>(Imm);}]> { + let ParserMatchClass = UImmAsmOperand<8, "Lsb000">; + let EncoderMethod = "getImmOpValue"; + let DecoderMethod = "decodeUImmOperand<8>"; + let OperandType = "OPERAND_UIMM8_LSB000"; + let MCOperandPredicate = [{ + int64_t Imm; + if (!MCOp.evaluateAsConstantImm(Imm)) + return false; + return isShiftedUInt<5, 3>(Imm); + }]; +} + +// A 9-bit signed immediate where the least significant bit is zero. +def simm9_lsb0 : Operand<OtherVT>, + ImmLeaf<XLenVT, [{return isShiftedInt<8, 1>(Imm);}]> { + let ParserMatchClass = SImmAsmOperand<9, "Lsb0">; + let PrintMethod = "printBranchOperand"; + let EncoderMethod = "getImmOpValueAsr1"; + let DecoderMethod = "decodeSImmOperandAndLsl1<9>"; + let MCOperandPredicate = [{ + int64_t Imm; + if (MCOp.evaluateAsConstantImm(Imm)) + return isShiftedInt<8, 1>(Imm); + return MCOp.isBareSymbolRef(); + }]; + let OperandType = "OPERAND_PCREL"; +} + +// A 9-bit unsigned immediate where the least significant three bits are zero. +def uimm9_lsb000 : RISCVOp, + ImmLeaf<XLenVT, [{return isShiftedUInt<6, 3>(Imm);}]> { + let ParserMatchClass = UImmAsmOperand<9, "Lsb000">; + let EncoderMethod = "getImmOpValue"; + let DecoderMethod = "decodeUImmOperand<9>"; + let OperandType = "OPERAND_UIMM9_LSB000"; + let MCOperandPredicate = [{ + int64_t Imm; + if (!MCOp.evaluateAsConstantImm(Imm)) + return false; + return isShiftedUInt<6, 3>(Imm); + }]; +} + +// A 10-bit unsigned immediate where the least significant two bits are zero +// and the immediate can't be zero. +def uimm10_lsb00nonzero : RISCVOp, + ImmLeaf<XLenVT, + [{return isShiftedUInt<8, 2>(Imm) && (Imm != 0);}]> { + let ParserMatchClass = UImmAsmOperand<10, "Lsb00NonZero">; + let EncoderMethod = "getImmOpValue"; + let DecoderMethod = "decodeUImmNonZeroOperand<10>"; + let OperandType = "OPERAND_UIMM10_LSB00_NONZERO"; + let MCOperandPredicate = [{ + int64_t Imm; + if (!MCOp.evaluateAsConstantImm(Imm)) + return false; + return isShiftedUInt<8, 2>(Imm) && (Imm != 0); + }]; +} + +// A 10-bit signed immediate where the least significant four bits are zero. +def simm10_lsb0000nonzero : RISCVOp, + ImmLeaf<XLenVT, + [{return (Imm != 0) && isShiftedInt<6, 4>(Imm);}]> { + let ParserMatchClass = SImmAsmOperand<10, "Lsb0000NonZero">; + let EncoderMethod = "getImmOpValue"; + let DecoderMethod = "decodeSImmNonZeroOperand<10>"; + let OperandType = "OPERAND_SIMM10_LSB0000_NONZERO"; + let MCOperandPredicate = [{ + int64_t Imm; + if (!MCOp.evaluateAsConstantImm(Imm)) + return false; + return isShiftedInt<6, 4>(Imm) && (Imm != 0); + }]; +} + +// A 12-bit signed immediate where the least significant bit is zero. +def simm12_lsb0 : Operand<XLenVT>, + ImmLeaf<XLenVT, [{return isShiftedInt<11, 1>(Imm);}]> { + let ParserMatchClass = SImmAsmOperand<12, "Lsb0">; + let PrintMethod = "printBranchOperand"; + let EncoderMethod = "getImmOpValueAsr1"; + let DecoderMethod = "decodeSImmOperandAndLsl1<12>"; + let MCOperandPredicate = [{ + int64_t Imm; + if (MCOp.evaluateAsConstantImm(Imm)) + return isShiftedInt<11, 1>(Imm); + return MCOp.isBareSymbolRef(); + }]; + let OperandType = "OPERAND_PCREL"; +} + // A 12-bit signed immediate which cannot fit in 6-bit signed immediate, // but even negative value fit in 12-bit. def simm12_no6 : ImmLeaf<XLenVT, [{ @@ -394,6 +534,10 @@ def ixlenimm_li_restricted : Operand<XLenVT> { // Standalone (codegen-only) immleaf patterns. +// A 12-bit signed immediate plus one where the imm range will be -2047~2048. +def simm12_plus1 : ImmLeaf<XLenVT, + [{return (isInt<12>(Imm) && Imm != -2048) || Imm == 2048;}]>; + // A 6-bit constant greater than 32. def uimm6gt32 : ImmLeaf<XLenVT, [{ return isUInt<6>(Imm) && Imm > 32; @@ -2119,6 +2263,7 @@ include "RISCVInstrInfoSFB.td" include "RISCVInstrInfoXCV.td" include "RISCVInstrInfoXwch.td" include "RISCVInstrInfoXqci.td" +include "RISCVInstrInfoXMips.td" //===----------------------------------------------------------------------===// // Global ISel diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td index ce994206cd785b..84ecb95212d3ae 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td @@ -94,131 +94,6 @@ def c_lui_imm : RISCVOp, }]; } -// A 7-bit unsigned immediate where the least significant two bits are zero. -def uimm7_lsb00 : RISCVOp, - ImmLeaf<XLenVT, [{return isShiftedUInt<5, 2>(Imm);}]> { - let ParserMatchClass = UImmAsmOperand<7, "Lsb00">; - let EncoderMethod = "getImmOpValue"; - let DecoderMethod = "decodeUImmOperand<7>"; - let OperandType = "OPERAND_UIMM7_LSB00"; - let MCOperandPredicate = [{ - int64_t Imm; - if (!MCOp.evaluateAsConstantImm(Imm)) - return false; - return isShiftedUInt<5, 2>(Imm); - }]; -} - -// A 8-bit unsigned immediate where the least significant two bits are zero. -def uimm8_lsb00 : RISCVOp, - ImmLeaf<XLenVT, [{return isShiftedUInt<6, 2>(Imm);}]> { - let ParserMatchClass = UImmAsmOperand<8, "Lsb00">; - let EncoderMethod = "getImmOpValue"; - let DecoderMethod = "decodeUImmOperand<8>"; - let OperandType = "OPERAND_UIMM8_LSB00"; - let MCOperandPredicate = [{ - int64_t Imm; - if (!MCOp.evaluateAsConstantImm(Imm)) - return false; - return isShiftedUInt<6, 2>(Imm); - }]; -} - -// A 8-bit unsigned immediate where the least significant three bits are zero. -def uimm8_lsb000 : RISCVOp, - ImmLeaf<XLenVT, [{return isShiftedUInt<5, 3>(Imm);}]> { - let ParserMatchClass = UImmAsmOperand<8, "Lsb000">; ... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/121394 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
