[clang] [llvm] [RISCV] Add Qualcomm uC Xqcicli (Conditional Load Immediate) extension (PR #121292)

[Craig Topper via cfe-commits]

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@@ -243,6 +253,24 @@ let Predicates = [HasVendorXqcilsm, IsRV32], 
DecoderNamespace = "Xqcilsm" in {
     def QC_LWMI : QCILoadMultiple<0b01, uimm5nonzero, "qc.lwmi">;
 } // Predicates = [HasVendorXqcilsm, IsRV32], DecoderNamespace = "Xqcilsm"
 
+let Predicates = [HasVendorXqcicli, IsRV32], DecoderNamespace = "Xqcicli" in {
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
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topperc wrote:

Can we put the `hasSideEffects = 0, mayLoad = 0, mayStore = 0` on the `QCILICC` 
class? Like was done for `QCIStoreMultiple`, `QCISELECTIICC`, etc?

https://github.com/llvm/llvm-project/pull/121292
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