llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-mc @llvm/pr-subscribers-clang-driver Author: Sudharsan Veeravalli (svs-quic) <details> <summary>Changes</summary> This extension adds 12 instructions that conditionally load an immediate value. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/latest This patch adds assembler only support. --- Patch is 20.50 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/121292.diff 11 Files Affected: - (modified) clang/test/Driver/print-supported-extensions-riscv.c (+1) - (modified) llvm/docs/RISCVUsage.rst (+3) - (modified) llvm/docs/ReleaseNotes.md (+2) - (modified) llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp (+3) - (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+8) - (modified) llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td (+28) - (modified) llvm/lib/TargetParser/RISCVISAInfo.cpp (+2-1) - (modified) llvm/test/CodeGen/RISCV/attributes.ll (+2) - (added) llvm/test/MC/RISCV/xqcicli-invalid.s (+232) - (added) llvm/test/MC/RISCV/xqcicli-valid.s (+59) - (modified) llvm/unittests/TargetParser/RISCVISAInfoTest.cpp (+3-1) ``````````diff diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index 8e46690cce5a63..395501eb85ccc3 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -190,6 +190,7 @@ // CHECK-NEXT: svukte 0.3 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses) // CHECK-NEXT: xqcia 0.2 'Xqcia' (Qualcomm uC Arithmetic Extension) // CHECK-NEXT: xqciac 0.2 'Xqciac' (Qualcomm uC Load-Store Address Calculation Extension) +// CHECK-NEXT: xqcicli 0.2 'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension) // CHECK-NEXT: xqcics 0.2 'Xqcics' (Qualcomm uC Conditional Select Extension) // CHECK-NEXT: xqcicsr 0.2 'Xqcicsr' (Qualcomm uC CSR Extension) // CHECK-NEXT: xqcilsm 0.2 'Xqcilsm' (Qualcomm uC Load Store Multiple Extension) diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 22600f5720553e..eaaad6c5168189 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -432,6 +432,9 @@ The current vendor extensions supported are: ``experimental-Xqciac`` LLVM implements `version 0.2 of the Qualcomm uC Load-Store Address Calculation extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32. +``experimental-Xqcicli`` + LLVM implements `version 0.2 of the Qualcomm uC Conditional Load Immediate extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32. + ``experimental-Xqcics`` LLVM implements `version 0.2 of the Qualcomm uC Conditional Select extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32. diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index 99a93b0467602d..be62a7e8696b4c 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -230,6 +230,8 @@ Changes to the RISC-V Backend extension. * Adds experimental assembler support for the Qualcomm uC 'Xqcilsm` (Load Store Multiple) extension. +* Adds experimental assembler support for the Qualcomm uC 'Xqcicli` (Conditional Load Immediate) + extension. Changes to the WebAssembly Backend ---------------------------------- diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 57443d3f38e3cb..30122831767f61 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -695,6 +695,9 @@ DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size, TRY_TO_DECODE_FEATURE( RISCV::FeatureVendorXqciac, DecoderTableXqciac32, "Qualcomm uC Load-Store Address Calculation custom opcode table"); + TRY_TO_DECODE_FEATURE( + RISCV::FeatureVendorXqcicli, DecoderTableXqcicli32, + "Qualcomm uC Conditional Load Immediate custom opcode table"); TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table"); return MCDisassembler::Fail; diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 916b140c5bde75..3885b95a8937a8 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1282,6 +1282,14 @@ def HasVendorXqciac AssemblerPredicate<(all_of FeatureVendorXqciac), "'Xqciac' (Qualcomm uC Load-Store Address Calculation Extension)">; +def FeatureVendorXqcicli + : RISCVExperimentalExtension<0, 2, + "Qualcomm uC Conditional Load Immediate Extension">; +def HasVendorXqcicli + : Predicate<"Subtarget->hasVendorXqcicli()">, + AssemblerPredicate<(all_of FeatureVendorXqcicli), + "'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension)">; + //===----------------------------------------------------------------------===// // LLVM specific features and extensions //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td index ca73fbccd9d2d2..e8562b2c944427 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td @@ -139,6 +139,16 @@ class QCIStoreMultiple<bits<2> funct2, DAGOperand InTyRs2, string opcodestr> let Inst{31-25} = {funct2, imm{6-2}}; } +class QCILICC<bits<3> funct3, bits<2> funct2, DAGOperand InTyRs2, string opcodestr> + : RVInstRBase<funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd_wb), + (ins GPRNoX0:$rd, GPRNoX0:$rs1, InTyRs2:$rs2, simm5:$simm), + opcodestr, "$rd, $rs1, $rs2, $simm"> { + let Constraints = "$rd = $rd_wb"; + bits<5> simm; + + let Inst{31-25} = {simm, funct2}; +} + //===----------------------------------------------------------------------===// // Instructions //===----------------------------------------------------------------------===// @@ -243,6 +253,24 @@ let Predicates = [HasVendorXqcilsm, IsRV32], DecoderNamespace = "Xqcilsm" in { def QC_LWMI : QCILoadMultiple<0b01, uimm5nonzero, "qc.lwmi">; } // Predicates = [HasVendorXqcilsm, IsRV32], DecoderNamespace = "Xqcilsm" +let Predicates = [HasVendorXqcicli, IsRV32], DecoderNamespace = "Xqcicli" in { +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { + def QC_LIEQ : QCILICC<0b000, 0b01, GPRNoX0, "qc.lieq">; + def QC_LINE : QCILICC<0b001, 0b01, GPRNoX0, "qc.line">; + def QC_LILT : QCILICC<0b100, 0b01, GPRNoX0, "qc.lilt">; + def QC_LIGE : QCILICC<0b101, 0b01, GPRNoX0, "qc.lige">; + def QC_LILTU : QCILICC<0b110, 0b01, GPRNoX0, "qc.liltu">; + def QC_LIGEU : QCILICC<0b111, 0b01, GPRNoX0, "qc.ligeu">; + + def QC_LIEQI : QCILICC<0b000, 0b11, simm5, "qc.lieqi">; + def QC_LINEI : QCILICC<0b001, 0b11, simm5, "qc.linei">; + def QC_LILTI : QCILICC<0b100, 0b11, simm5, "qc.lilti">; + def QC_LIGEI : QCILICC<0b101, 0b11, simm5, "qc.ligei">; + def QC_LILTUI : QCILICC<0b110, 0b11, uimm5, "qc.liltui">; + def QC_LIGEUI : QCILICC<0b111, 0b11, uimm5, "qc.ligeui">; +} // hasSideEffects = 0, mayLoad = 0, mayStore = 0 +} // Predicates = [HasVendorXqcicli, IsRV32], DecoderNamespace = "Xqcicli" + //===----------------------------------------------------------------------===// // Aliases //===----------------------------------------------------------------------===// diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp b/llvm/lib/TargetParser/RISCVISAInfo.cpp index e4e459a77b5f8f..4f403e9fb6f574 100644 --- a/llvm/lib/TargetParser/RISCVISAInfo.cpp +++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp @@ -742,7 +742,8 @@ Error RISCVISAInfo::checkDependency() { bool HasZvl = MinVLen != 0; bool HasZcmt = Exts.count("zcmt") != 0; static constexpr StringLiteral XqciExts[] = { - {"xqcia"}, {"xqciac"}, {"xqcics"}, {"xqcicsr"}, {"xqcilsm"}, {"xqcisls"}}; + {"xqcia"}, {"xqciac"}, {"xqcicli"}, {"xqcics"}, + {"xqcicsr"}, {"xqcilsm"}, {"xqcisls"}}; if (HasI && HasE) return getIncompatibleError("i", "e"); diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 3f2b2c94707835..bcf945470d85b3 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -83,6 +83,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+xwchc %s -o - | FileCheck --check-prefix=RV32XWCHC %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcia %s -o - | FileCheck --check-prefix=RV32XQCIA %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqciac %s -o - | FileCheck --check-prefix=RV32XQCIAC %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicli %s -o - | FileCheck --check-prefix=RV32XQCICLI %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcics %s -o - | FileCheck --check-prefix=RV32XQCICS %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicsr %s -o - | FileCheck --check-prefix=RV32XQCICSR %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilsm %s -o - | FileCheck --check-prefix=RV32XQCILSM %s @@ -393,6 +394,7 @@ ; RV32XWCHC: .attribute 5, "rv32i2p1_xwchc2p2" ; RV32XQCIA: .attribute 5, "rv32i2p1_xqcia0p2" ; RV32XQCIAC: .attribute 5, "rv32i2p1_zca1p0_xqciac0p2" +; RV32XQCICLI: .attribute 5, "rv32i2p1_xqcicli0p2" ; RV32XQCICS: .attribute 5, "rv32i2p1_xqcics0p2" ; RV32XQCICSR: .attribute 5, "rv32i2p1_xqcicsr0p2" ; RV32XQCILSM: .attribute 5, "rv32i2p1_xqcilsm0p2" diff --git a/llvm/test/MC/RISCV/xqcicli-invalid.s b/llvm/test/MC/RISCV/xqcicli-invalid.s new file mode 100644 index 00000000000000..7ee92ec4cbc012 --- /dev/null +++ b/llvm/test/MC/RISCV/xqcicli-invalid.s @@ -0,0 +1,232 @@ +# Xqcicli - Qualcomm uC Conditional Load Immediate Instructions +# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-xqcicli < %s 2>&1 \ +# RUN: | FileCheck -check-prefixes=CHECK,CHECK-PLUS %s +# RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqcicli < %s 2>&1 \ +# RUN: | FileCheck -check-prefixes=CHECK,CHECK-MINUS %s + +# CHECK: :[[@LINE+1]]:9: error: invalid operand for instruction +qc.lieq x0, x4, x6, 10 + +# CHECK: :[[@LINE+1]]:13: error: invalid operand for instruction +qc.lieq x2, x0, x6, 10 + +# CHECK: :[[@LINE+1]]:17: error: invalid operand for instruction +qc.lieq x2, x4, x0, 10 + +# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction +qc.lieq x2, x4, x6 + +# CHECK-PLUS: :[[@LINE+1]]:21: error: immediate must be an integer in the range [-16, 15] +qc.lieq x2, x4, x6, 40 + +# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension) +qc.lieq x2, x4, x6, 10 + + +# CHECK: :[[@LINE+1]]:9: error: invalid operand for instruction +qc.lige x0, x8, x20, 2 + +# CHECK: :[[@LINE+1]]:13: error: invalid operand for instruction +qc.lige x4, x0, x20, 2 + +# CHECK: :[[@LINE+1]]:17: error: invalid operand for instruction +qc.lige x4, x8, x0, 2 + +# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction +qc.lige x4, x8, x20 + +# CHECK-PLUS: :[[@LINE+1]]:22: error: immediate must be an integer in the range [-16, 15] +qc.lige x4, x8, x20, -18 + +# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension) +qc.lige x4, x8, x20, 2 + + +# CHECK: :[[@LINE+1]]:9: error: invalid operand for instruction +qc.lilt x0, x9, x10, 3 + +# CHECK: :[[@LINE+1]]:14: error: invalid operand for instruction +qc.lilt x19, x0, x10, 3 + +# CHECK: :[[@LINE+1]]:18: error: invalid operand for instruction +qc.lilt x19, x9, x0, 3 + +# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction +qc.lilt x19, x9, x10 + +# CHECK-PLUS: :[[@LINE+1]]:23: error: immediate must be an integer in the range [-16, 15] +qc.lilt x19, x9, x10, 39 + +# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension) +qc.lilt x19, x9, x10, 3 + + +# CHECK: :[[@LINE+1]]:9: error: invalid operand for instruction +qc.line x0, x14, x6, 10 + +# CHECK: :[[@LINE+1]]:14: error: invalid operand for instruction +qc.line x18, x0, x6, 10 + +# CHECK: :[[@LINE+1]]:19: error: invalid operand for instruction +qc.line x18, x14, x0, 10 + +# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction +qc.line x18, x14, x6 + +# CHECK-PLUS: :[[@LINE+1]]:23: error: immediate must be an integer in the range [-16, 15] +qc.line x18, x14, x6, 100 + +# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension) +qc.line x18, x14, x6, 10 + + +# CHECK: :[[@LINE+1]]:10: error: invalid operand for instruction +qc.ligeu x0, x4, x6, 10 + +# CHECK: :[[@LINE+1]]:14: error: invalid operand for instruction +qc.ligeu x2, x0, x6, 10 + +# CHECK: :[[@LINE+1]]:18: error: invalid operand for instruction +qc.ligeu x2, x4, x0, 10 + +# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction +qc.ligeu x2, x4, x6 + +# CHECK-PLUS: :[[@LINE+1]]:22: error: immediate must be an integer in the range [-16, 15] +qc.ligeu x2, x4, x6, 70 + +# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension) +qc.ligeu x2, x4, x6, 10 + + +# CHECK: :[[@LINE+1]]:10: error: invalid operand for instruction +qc.liltu x0, x19, x12, 13 + +# CHECK: :[[@LINE+1]]:14: error: invalid operand for instruction +qc.liltu x1, x0, x12, 13 + +# CHECK: :[[@LINE+1]]:19: error: invalid operand for instruction +qc.liltu x1, x19, x0, 13 + +# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction +qc.liltu x1, x19, x12 + +# CHECK-PLUS: :[[@LINE+1]]:24: error: immediate must be an integer in the range [-16, 15] +qc.liltu x1, x19, x12, 73 + +# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension) +qc.liltu x1, x19, x12, 13 + + +# CHECK: :[[@LINE+1]]:10: error: invalid operand for instruction +qc.lieqi x0, x1, 15, 12 + +# CHECK: :[[@LINE+1]]:14: error: invalid operand for instruction +qc.lieqi x7, x0, 15, 12 + +# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction +qc.lieqi x7, x1, 15 + +# CHECK-PLUS: :[[@LINE+1]]:18: error: immediate must be an integer in the range [-16, 15] +qc.lieqi x7, x1, 25, 12 + +# CHECK-PLUS: :[[@LINE+1]]:22: error: immediate must be an integer in the range [-16, 15] +qc.lieqi x7, x1, 15, -22 + +# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension) +qc.lieqi x7, x1, 15, 12 + + +# CHECK: :[[@LINE+1]]:10: error: invalid operand for instruction +qc.ligei x0, x11, -4, 9 + +# CHECK: :[[@LINE+1]]:15: error: invalid operand for instruction +qc.ligei x17, x0, -4, 9 + +# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction +qc.ligei x17, x11, -4 + +# CHECK-PLUS: :[[@LINE+1]]:20: error: immediate must be an integer in the range [-16, 15] +qc.ligei x17, x11, -24, 9 + +# CHECK-PLUS: :[[@LINE+1]]:24: error: immediate must be an integer in the range [-16, 15] +qc.ligei x17, x11, -4, 59 + +# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension) +qc.ligei x17, x11, -4, 9 + + +# CHECK: :[[@LINE+1]]:10: error: invalid operand for instruction +qc.lilti x0, x11, -14, 2 + +# CHECK: :[[@LINE+1]]:14: error: invalid operand for instruction +qc.lilti x9, x0, -14, 2 + +# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction +qc.lilti x9, x11, -14 + +# CHECK-PLUS: :[[@LINE+1]]:19: error: immediate must be an integer in the range [-16, 15] +qc.lilti x9, x11, -84, 2 + +# CHECK-PLUS: :[[@LINE+1]]:24: error: immediate must be an integer in the range [-16, 15] +qc.lilti x9, x11, -14, 52 + +# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension) +qc.lilti x9, x11, -14, 2 + + +# CHECK: :[[@LINE+1]]:10: error: invalid operand for instruction +qc.linei x0, x1, 10, 12 + +# CHECK: :[[@LINE+1]]:14: error: invalid operand for instruction +qc.linei x5, x0, 10, 12 + +# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction +qc.linei x5, x1, 10 + +# CHECK-PLUS: :[[@LINE+1]]:18: error: immediate must be an integer in the range [-16, 15] +qc.linei x5, x1, 130, 12 + +# CHECK-PLUS: :[[@LINE+1]]:22: error: immediate must be an integer in the range [-16, 15] +qc.linei x5, x1, 10, 124 + +# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension) +qc.linei x5, x1, 10, 12 + + +# CHECK: :[[@LINE+1]]:11: error: invalid operand for instruction +qc.ligeui x0, x12, 7, -12 + +# CHECK: :[[@LINE+1]]:15: error: invalid operand for instruction +qc.ligeui x2, x0, 7, -12 + +# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction +qc.ligeui x2, x12, 7 + +# CHECK-PLUS: :[[@LINE+1]]:20: error: immediate must be an integer in the range [0, 31] +qc.ligeui x2, x12, -7, -12 + +# CHECK-PLUS: :[[@LINE+1]]:23: error: immediate must be an integer in the range [-16, 15] +qc.ligeui x2, x12, 7, -17 + +# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension) +qc.ligeui x2, x12, 7, -12 + + +# CHECK: :[[@LINE+1]]:11: error: invalid operand for instruction +qc.liltui x0, x25, 31, 12 + +# CHECK: :[[@LINE+1]]:15: error: invalid operand for instruction +qc.liltui x3, x0, 31, 12 + +# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction +qc.liltui x3, x25, 31 + +# CHECK-PLUS: :[[@LINE+1]]:20: error: immediate must be an integer in the range [0, 31] +qc.liltui x3, x25, 32, 12 + +# CHECK-PLUS: :[[@LINE+1]]:24: error: immediate must be an integer in the range [-16, 15] +qc.liltui x3, x25, 31, 112 + +# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension) +qc.liltui x3, x25, 31, 12 diff --git a/llvm/test/MC/RISCV/xqcicli-valid.s b/llvm/test/MC/RISCV/xqcicli-valid.s new file mode 100644 index 00000000000000..404bfdf7bce26e --- /dev/null +++ b/llvm/test/MC/RISCV/xqcicli-valid.s @@ -0,0 +1,59 @@ +# Xqcicli - Qualcomm uC Conditional Load Immediate Extension +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcicli -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcicli < %s \ +# RUN: | llvm-objdump --mattr=+experimental-xqcicli -M no-aliases --no-print-imm-hex -d - \ +# RUN: | FileCheck -check-prefix=CHECK-INST %s +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcicli -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcicli < %s \ +# RUN: | llvm-objdump --mattr=+experimental-xqcicli --no-print-imm-hex -d - \ +# RUN: | FileCheck -check-prefix=CHECK-INST %s + +# CHECK-INST: qc.lieq sp, tp, t1, 10 +# CHECK-ENC: encoding: [0x5b,0x01,0x62,0x52] +qc.lieq x2, x4, x6, 10 + +# CHECK-INST: qc.lieqi t2, ra, 15, 12 +# CHECK-ENC: encoding: [0xdb,0x83,0xf0,0x66] +qc.lieqi x7, x1, 15, 12 + +# CHECK-INST: qc.lige tp, s0, s4, 2 +# CHECK-ENC: encoding: [0x5b,0x52,0x44,0x13] +qc.lige x4, x8, x20, 2 + +# CHECK-INST: qc.ligei a7, a1, -4, 9 +# CHECK-ENC: encoding: [0xdb,0xd8,0xc5,0x4f] +qc.ligei x17, x11, -4, 9 + +# CHECK-INST: qc.ligeu sp, tp, t1, 10 +# CHECK-ENC: encoding: [0x5b,0x71,0x62,0x52] +qc.ligeu x2, x4, x6, 10 + +# CHECK-INST: qc.ligeui sp, a2, 7, -12 +# CHECK-ENC: encoding: [0x5b,0x71,0x76,0xa6] +qc.ligeui x2, x12, 7, -12 + +# CHECK-INST: qc.lilt s3, s1, a0, 3 +# CHECK-ENC: encoding: [0xdb,0xc9,0xa4,0x1a] +qc.lilt x19, x9, x10, 3 + +# CHECK-INST: qc.lilti s1, a1, -14, 2 +# CHECK-ENC: encoding: [0xdb,0xc4,0x25,0x17] +qc.lilti x9, x11, -14, 2 + +# CHECK-INST: qc.liltu ra, s3, a2, 13 +# CHECK-ENC: encoding: [0xdb,0xe0,0xc9,0x6a] +qc.liltu x1, x19, x12, 13 + +# CHECK-INST: qc.liltui gp, s9, 31, 12 +# CHECK-ENC: encoding: [0xdb,0xe1,0xfc,0x67] +qc.liltui x3, x25, 31, 12 + +# CHECK-INST: qc.line s2, a4, t1, 10 +# CHECK-ENC: encoding: [0x5b,0x19,0x67,0x52] +qc.line x18, x14, x6, 10 + +# CHECK-INST: qc.linei t0, ra, 10, 12 +# CHECK-ENC: encoding: [0xdb,0x92,0xa0,0x66] +qc.linei x5, x1, 10, 12 diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index 176cf82ac34b13..f631f26cf482eb 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -655,7 +655,8 @@ TEST(ParseArchString, RejectsConflictingExtensions) { for (StringRef Input : {"rv64i_xqcisls0p2", "rv64i_xqcia0p2", "rv64i_xqciac0p2", - "rv64i_xqcicsr0p2", "rv64i_xqcilsm0p2", "rv64i_xqcics0p2"}) { + ... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/121292 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
