llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-clang Author: Alexey Gerenkov (gerekon) <details> <summary>Changes</summary> This PR implements support for generic Xtensa target in CLang. --- Patch is 28.35 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/118008.diff 9 Files Affected: - (modified) clang/include/clang/Basic/TargetInfo.h (+4-1) - (modified) clang/lib/AST/ASTContext.cpp (+47) - (modified) clang/lib/Basic/CMakeLists.txt (+1) - (modified) clang/lib/Basic/Targets.cpp (+4) - (added) clang/lib/Basic/Targets/Xtensa.cpp (+62) - (added) clang/lib/Basic/Targets/Xtensa.h (+141) - (modified) clang/lib/Driver/ToolChains/CommonArgs.cpp (+5) - (modified) clang/test/Preprocessor/init.c (+272) - (modified) clang/test/Preprocessor/stdint.c (+107) ``````````diff diff --git a/clang/include/clang/Basic/TargetInfo.h b/clang/include/clang/Basic/TargetInfo.h index 9cd23d123f2bac..97444ef28a66d8 100644 --- a/clang/include/clang/Basic/TargetInfo.h +++ b/clang/include/clang/Basic/TargetInfo.h @@ -358,7 +358,10 @@ class TargetInfo : public TransferrableTargetInfo, // void *__saved_reg_area_end_pointer; // void *__overflow_area_pointer; //} va_list; - HexagonBuiltinVaList + HexagonBuiltinVaList, + + // Tensilica Xtensa + XtensaABIBuiltinVaList }; protected: diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp index 80e8c5b9df58e7..0f2df53d07e086 100644 --- a/clang/lib/AST/ASTContext.cpp +++ b/clang/lib/AST/ASTContext.cpp @@ -9727,6 +9727,51 @@ static TypedefDecl *CreateHexagonBuiltinVaListDecl(const ASTContext *Context) { return Context->buildImplicitTypedef(VaListTagArrayType, "__builtin_va_list"); } +static TypedefDecl * +CreateXtensaABIBuiltinVaListDecl(const ASTContext *Context) { + // typedef struct __va_list_tag { + RecordDecl *VaListTagDecl; + + VaListTagDecl = Context->buildImplicitRecord("__va_list_tag"); + VaListTagDecl->startDefinition(); + + const size_t NumFields = 3; + QualType FieldTypes[NumFields]; + const char *FieldNames[NumFields]; + + // int* __va_stk; + FieldTypes[0] = Context->getPointerType(Context->IntTy); + FieldNames[0] = "__va_stk"; + + // int* __va_reg; + FieldTypes[1] = Context->getPointerType(Context->IntTy); + FieldNames[1] = "__va_reg"; + + // int __va_ndx; + FieldTypes[2] = Context->IntTy; + FieldNames[2] = "__va_ndx"; + + // Create fields + for (unsigned i = 0; i < NumFields; ++i) { + FieldDecl *Field = FieldDecl::Create( + *Context, VaListTagDecl, SourceLocation(), SourceLocation(), + &Context->Idents.get(FieldNames[i]), FieldTypes[i], /*TInfo=*/nullptr, + /*BitWidth=*/nullptr, + /*Mutable=*/false, ICIS_NoInit); + Field->setAccess(AS_public); + VaListTagDecl->addDecl(Field); + } + VaListTagDecl->completeDefinition(); + Context->VaListTagDecl = VaListTagDecl; + QualType VaListTagType = Context->getRecordType(VaListTagDecl); + + // } __va_list_tag; + TypedefDecl *VaListTagTypedefDecl = + Context->buildImplicitTypedef(VaListTagType, "__builtin_va_list"); + + return VaListTagTypedefDecl; +} + static TypedefDecl *CreateVaListDecl(const ASTContext *Context, TargetInfo::BuiltinVaListKind Kind) { switch (Kind) { @@ -9748,6 +9793,8 @@ static TypedefDecl *CreateVaListDecl(const ASTContext *Context, return CreateSystemZBuiltinVaListDecl(Context); case TargetInfo::HexagonBuiltinVaList: return CreateHexagonBuiltinVaListDecl(Context); + case TargetInfo::XtensaABIBuiltinVaList: + return CreateXtensaABIBuiltinVaListDecl(Context); } llvm_unreachable("Unhandled __builtin_va_list type kind"); diff --git a/clang/lib/Basic/CMakeLists.txt b/clang/lib/Basic/CMakeLists.txt index e11e1ac4a6fa63..331dfbb3f4b67e 100644 --- a/clang/lib/Basic/CMakeLists.txt +++ b/clang/lib/Basic/CMakeLists.txt @@ -120,6 +120,7 @@ add_clang_library(clangBasic Targets/WebAssembly.cpp Targets/X86.cpp Targets/XCore.cpp + Targets/Xtensa.cpp TokenKinds.cpp TypeTraits.cpp Version.cpp diff --git a/clang/lib/Basic/Targets.cpp b/clang/lib/Basic/Targets.cpp index 0021d33c45d7c9..3ef99acdc2e323 100644 --- a/clang/lib/Basic/Targets.cpp +++ b/clang/lib/Basic/Targets.cpp @@ -40,6 +40,7 @@ #include "Targets/WebAssembly.h" #include "Targets/X86.h" #include "Targets/XCore.h" +#include "Targets/Xtensa.h" #include "clang/Basic/Diagnostic.h" #include "clang/Basic/DiagnosticFrontend.h" #include "llvm/ADT/StringExtras.h" @@ -737,6 +738,9 @@ std::unique_ptr<TargetInfo> AllocateTarget(const llvm::Triple &Triple, default: return std::make_unique<LoongArch64TargetInfo>(Triple, Opts); } + + case llvm::Triple::xtensa: + return std::make_unique<XtensaTargetInfo>(Triple, Opts); } } } // namespace targets diff --git a/clang/lib/Basic/Targets/Xtensa.cpp b/clang/lib/Basic/Targets/Xtensa.cpp new file mode 100644 index 00000000000000..b46db6bfbd67ac --- /dev/null +++ b/clang/lib/Basic/Targets/Xtensa.cpp @@ -0,0 +1,62 @@ +//===--- Xtensa.cpp - Implement Xtensa target feature support -------------===// +// +// The LLVM Compiler Infrastructure +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file implements Xtensa TargetInfo objects. +// +//===----------------------------------------------------------------------===// + +#include "Xtensa.h" +#include "clang/Basic/Builtins.h" +#include "clang/Basic/MacroBuilder.h" +#include "clang/Basic/TargetBuiltins.h" + +using namespace clang; +using namespace clang::targets; + +void XtensaTargetInfo::getTargetDefines(const LangOptions &Opts, + MacroBuilder &Builder) const { + Builder.defineMacro("__xtensa__"); + Builder.defineMacro("__XTENSA__"); + if (BigEndian) + Builder.defineMacro("__XTENSA_EB__"); + else + Builder.defineMacro("__XTENSA_EL__"); + if (HasWindowed) + Builder.defineMacro("__XTENSA_WINDOWED_ABI__"); + else + Builder.defineMacro("__XTENSA_CALL0_ABI__"); + if (!HasFP) + Builder.defineMacro("__XTENSA_SOFT_FLOAT__"); + Builder.defineMacro("__XCHAL_HAVE_BE", BigEndian ? "1" : "0"); + Builder.defineMacro("__XCHAL_HAVE_DENSITY", HasDensity ? "1" : "0"); + Builder.defineMacro("__XCHAL_HAVE_MAC16", HasMAC16 ? "1" : "0"); + Builder.defineMacro("__XCHAL_HAVE_MUL16", HasMul16 ? "1" : "0"); + Builder.defineMacro("__XCHAL_HAVE_MUL32", HasMul32 ? "1" : "0"); + Builder.defineMacro("__XCHAL_HAVE_MUL32_HIGH", HasMul32High ? "1" : "0"); + Builder.defineMacro("__XCHAL_HAVE_DIV32", HasDiv32 ? "1" : "0"); + Builder.defineMacro("__XCHAL_HAVE_NSA", HasNSA ? "1" : "0"); + Builder.defineMacro("__XCHAL_HAVE_MINMAX", HasMINMAX ? "1" : "0"); + Builder.defineMacro("__XCHAL_HAVE_SEXT", HasSEXT ? "1" : "0"); + Builder.defineMacro("__XCHAL_HAVE_LOOPS", HasLoop ? "1" : "0"); + Builder.defineMacro("__XCHAL_HAVE_THREADPTR", HasTHREADPTR ? "1" : "0"); + Builder.defineMacro("__XCHAL_HAVE_S32C1I", HasS32C1I ? "1" : "0"); + Builder.defineMacro("__XCHAL_HAVE_BOOLEANS", HasBoolean ? "1" : "0"); + Builder.defineMacro("__XCHAL_HAVE_FP", HasFP ? "1" : "0"); + Builder.defineMacro("__XCHAL_HAVE_FP_DIV", HasFP ? "1" : "0"); + Builder.defineMacro("__XCHAL_HAVE_FP_RECIP", HasFP ? "1" : "0"); + Builder.defineMacro("__XCHAL_HAVE_FP_SQRT", HasFP ? "1" : "0"); + Builder.defineMacro("__XCHAL_HAVE_FP_RSQRT", HasFP ? "1" : "0"); + Builder.defineMacro("__XCHAL_HAVE_FP_POSTINC", HasFP ? "1" : "0"); + Builder.defineMacro("__XCHAL_HAVE_WINDOWED", HasWindowed ? "1" : "0"); + Builder.defineMacro("__XCHAL_HAVE_DEBUG", HasDebug ? "1" : "0"); + Builder.defineMacro("__XCHAL_HAVE_ABS"); // core arch + Builder.defineMacro("__XCHAL_HAVE_ADDX"); // core arch + Builder.defineMacro("__XCHAL_HAVE_L32R"); // core arch +} diff --git a/clang/lib/Basic/Targets/Xtensa.h b/clang/lib/Basic/Targets/Xtensa.h new file mode 100644 index 00000000000000..d850980bfc33e1 --- /dev/null +++ b/clang/lib/Basic/Targets/Xtensa.h @@ -0,0 +1,141 @@ +//===--- Xtensa.h - Declare Xtensa target feature support -------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file declares Xtensa TargetInfo objects. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_XTENSA_H +#define LLVM_CLANG_LIB_BASIC_TARGETS_XTENSA_H + +#include "clang/Basic/TargetInfo.h" +#include "clang/Basic/TargetOptions.h" +#include "llvm/ADT/StringSwitch.h" +#include "llvm/Support/Compiler.h" +#include "llvm/TargetParser/Triple.h" + +#include "clang/Basic/Builtins.h" +#include "clang/Basic/MacroBuilder.h" +#include "clang/Basic/TargetBuiltins.h" + +namespace clang { +namespace targets { + +class LLVM_LIBRARY_VISIBILITY XtensaTargetInfo : public TargetInfo { + static const Builtin::Info BuiltinInfo[]; + +protected: + std::string CPU; + bool HasFP = false; + bool HasWindowed = false; + bool HasBoolean = false; + bool HasHIFI3 = false; + bool HasDensity = false; + bool HasLoop = false; + bool HasSEXT = false; + bool HasNSA = false; + bool HasCLAPMS = false; + bool HasMINMAX = false; + bool HasMul16 = false; + bool HasMul32 = false; + bool HasMul32High = false; + bool HasDiv32 = false; + bool HasMAC16 = false; + bool HasS32C1I = false; + bool HasTHREADPTR = false; + bool HasExtendedL32R = false; + bool HasATOMCTL = false; + bool HasMEMCTL = false; + bool HasDebug = false; + bool HasException = false; + bool HasHighPriInterrupts = false; + bool HasCoprocessor = false; + bool HasInterrupt = false; + bool HasRelocatableVector = false; + bool HasTimerInt = false; + bool HasPRID = false; + bool HasRegionProtection = false; + bool HasMiscSR = false; + +public: + XtensaTargetInfo(const llvm::Triple &Triple, const TargetOptions &) + : TargetInfo(Triple) { + BigEndian = false; + NoAsmVariants = true; + LongLongAlign = 64; + SuitableAlign = 32; + DoubleAlign = LongDoubleAlign = 64; + SizeType = UnsignedInt; + PtrDiffType = SignedInt; + IntPtrType = SignedInt; + WCharType = SignedInt; + WIntType = UnsignedInt; + UseZeroLengthBitfieldAlignment = true; + MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; + resetDataLayout("e-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32"); + } + + void getTargetDefines(const LangOptions &Opts, + MacroBuilder &Builder) const override; + + ArrayRef<Builtin::Info> getTargetBuiltins() const override { + return std::nullopt; + } + + BuiltinVaListKind getBuiltinVaListKind() const override { + + return TargetInfo::XtensaABIBuiltinVaList; + } + + std::string_view getClobbers() const override { return ""; } + + ArrayRef<const char *> getGCCRegNames() const override { + static const char *const GCCRegNames[] = { + // General register name + "a0", "sp", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "a8", "a9", "a10", + "a11", "a12", "a13", "a14", "a15", + // Special register name + "sar"}; + return llvm::ArrayRef(GCCRegNames); + } + + ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { + return std::nullopt; + } + + bool validateAsmConstraint(const char *&Name, + TargetInfo::ConstraintInfo &Info) const override { + switch (*Name) { + default: + return false; + case 'a': + Info.setAllowsRegister(); + return true; + } + return false; + } + + int getEHDataRegisterNumber(unsigned RegNo) const override { + return (RegNo < 2) ? RegNo : -1; + } + + bool isValidCPUName(StringRef Name) const override { + return llvm::StringSwitch<bool>(Name).Case("generic", true).Default(false); + } + + bool setCPU(const std::string &Name) override { + CPU = Name; + return isValidCPUName(Name); + } +}; + +} // namespace targets +} // namespace clang +#endif // LLVM_CLANG_LIB_BASIC_TARGETS_XTENSA_H diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp b/clang/lib/Driver/ToolChains/CommonArgs.cpp index 8d977149e62485..49298c5c6cb8fb 100644 --- a/clang/lib/Driver/ToolChains/CommonArgs.cpp +++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp @@ -671,6 +671,11 @@ std::string tools::getCPUName(const Driver &D, const ArgList &Args, case llvm::Triple::loongarch32: case llvm::Triple::loongarch64: return loongarch::getLoongArchTargetCPU(Args, T); + + case llvm::Triple::xtensa: + if (const Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) + return A->getValue(); + return ""; } } diff --git a/clang/test/Preprocessor/init.c b/clang/test/Preprocessor/init.c index 05225c120b13de..ead349dec3cf18 100644 --- a/clang/test/Preprocessor/init.c +++ b/clang/test/Preprocessor/init.c @@ -2742,3 +2742,275 @@ // RISCV64-LINUX: #define __unix__ 1 // RISCV64-LINUX: #define linux 1 // RISCV64-LINUX: #define unix 1 + +// RUN: %clang_cc1 -E -dM -ffreestanding -fgnuc-version=4.2.1 -triple=xtensa < /dev/null \ +// RUN: | FileCheck -match-full-lines -check-prefix=XTENSA %s +// XTENSA: #define _ILP32 1 +// XTENSA: #define __ATOMIC_ACQUIRE 2 +// XTENSA: #define __ATOMIC_ACQ_REL 4 +// XTENSA: #define __ATOMIC_CONSUME 1 +// XTENSA: #define __ATOMIC_RELAXED 0 +// XTENSA: #define __ATOMIC_RELEASE 3 +// XTENSA: #define __ATOMIC_SEQ_CST 5 +// XTENSA: #define __BIGGEST_ALIGNMENT__ 4 +// XTENSA: #define __BITINT_MAXWIDTH__ 128 +// XTENSA: #define __BOOL_WIDTH__ 1 +// XTENSA: #define __BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__ +// XTENSA: #define __CHAR16_TYPE__ unsigned short +// XTENSA: #define __CHAR32_TYPE__ unsigned int +// XTENSA: #define __CHAR_BIT__ 8 +// XTENSA: #define __CLANG_ATOMIC_BOOL_LOCK_FREE 2 +// XTENSA: #define __CLANG_ATOMIC_CHAR16_T_LOCK_FREE 2 +// XTENSA: #define __CLANG_ATOMIC_CHAR32_T_LOCK_FREE 2 +// XTENSA: #define __CLANG_ATOMIC_CHAR_LOCK_FREE 2 +// XTENSA: #define __CLANG_ATOMIC_INT_LOCK_FREE 2 +// XTENSA: #define __CLANG_ATOMIC_LLONG_LOCK_FREE 1 +// XTENSA: #define __CLANG_ATOMIC_LONG_LOCK_FREE 2 +// XTENSA: #define __CLANG_ATOMIC_POINTER_LOCK_FREE 2 +// XTENSA: #define __CLANG_ATOMIC_SHORT_LOCK_FREE 2 +// XTENSA: #define __CLANG_ATOMIC_WCHAR_T_LOCK_FREE 2 +// XTENSA: #define __CONSTANT_CFSTRINGS__ 1 +// XTENSA: #define __DBL_DECIMAL_DIG__ 17 +// XTENSA: #define __DBL_DENORM_MIN__ 4.9406564584124654e-324 +// XTENSA: #define __DBL_DIG__ 15 +// XTENSA: #define __DBL_EPSILON__ 2.2204460492503131e-16 +// XTENSA: #define __DBL_HAS_DENORM__ 1 +// XTENSA: #define __DBL_HAS_INFINITY__ 1 +// XTENSA: #define __DBL_HAS_QUIET_NAN__ 1 +// XTENSA: #define __DBL_MANT_DIG__ 53 +// XTENSA: #define __DBL_MAX_10_EXP__ 308 +// XTENSA: #define __DBL_MAX_EXP__ 1024 +// XTENSA: #define __DBL_MAX__ 1.7976931348623157e+308 +// XTENSA: #define __DBL_MIN_10_EXP__ (-307) +// XTENSA: #define __DBL_MIN_EXP__ (-1021) +// XTENSA: #define __DBL_MIN__ 2.2250738585072014e-308 +// XTENSA: #define __DBL_NORM_MAX__ 1.7976931348623157e+308 +// XTENSA: #define __DECIMAL_DIG__ __LDBL_DECIMAL_DIG__ +// XTENSA: #define __ELF__ 1 +// XTENSA: #define __FINITE_MATH_ONLY__ 0 +// XTENSA: #define __FLT_DECIMAL_DIG__ 9 +// XTENSA: #define __FLT_DENORM_MIN__ 1.40129846e-45F +// XTENSA: #define __FLT_DIG__ 6 +// XTENSA: #define __FLT_EPSILON__ 1.19209290e-7F +// XTENSA: #define __FLT_HAS_DENORM__ 1 +// XTENSA: #define __FLT_HAS_INFINITY__ 1 +// XTENSA: #define __FLT_HAS_QUIET_NAN__ 1 +// XTENSA: #define __FLT_MANT_DIG__ 24 +// XTENSA: #define __FLT_MAX_10_EXP__ 38 +// XTENSA: #define __FLT_MAX_EXP__ 128 +// XTENSA: #define __FLT_MAX__ 3.40282347e+38F +// XTENSA: #define __FLT_MIN_10_EXP__ (-37) +// XTENSA: #define __FLT_MIN_EXP__ (-125) +// XTENSA: #define __FLT_MIN__ 1.17549435e-38F +// XTENSA: #define __FLT_NORM_MAX__ 3.40282347e+38F +// XTENSA: #define __FLT_RADIX__ 2 +// XTENSA: #define __FPCLASS_NEGINF 0x0004 +// XTENSA: #define __FPCLASS_NEGNORMAL 0x0008 +// XTENSA: #define __FPCLASS_NEGSUBNORMAL 0x0010 +// XTENSA: #define __FPCLASS_NEGZERO 0x0020 +// XTENSA: #define __FPCLASS_POSINF 0x0200 +// XTENSA: #define __FPCLASS_POSNORMAL 0x0100 +// XTENSA: #define __FPCLASS_POSSUBNORMAL 0x0080 +// XTENSA: #define __FPCLASS_POSZERO 0x0040 +// XTENSA: #define __FPCLASS_QNAN 0x0002 +// XTENSA: #define __FPCLASS_SNAN 0x0001 +// XTENSA: #define __GCC_ATOMIC_BOOL_LOCK_FREE 2 +// XTENSA: #define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 2 +// XTENSA: #define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 2 +// XTENSA: #define __GCC_ATOMIC_CHAR_LOCK_FREE 2 +// XTENSA: #define __GCC_ATOMIC_INT_LOCK_FREE 2 +// XTENSA: #define __GCC_ATOMIC_LLONG_LOCK_FREE 1 +// XTENSA: #define __GCC_ATOMIC_LONG_LOCK_FREE 2 +// XTENSA: #define __GCC_ATOMIC_POINTER_LOCK_FREE 2 +// XTENSA: #define __GCC_ATOMIC_SHORT_LOCK_FREE 2 +// XTENSA: #define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1 +// XTENSA: #define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2 +// XTENSA: #define __GCC_CONSTRUCTIVE_SIZE 64 +// XTENSA: #define __GCC_DESTRUCTIVE_SIZE 64 +// XTENSA: #define __GNUC_MINOR__ {{.*}} +// XTENSA: #define __GNUC_PATCHLEVEL__ {{.*}} +// XTENSA: #define __GNUC_STDC_INLINE__ 1 +// XTENSA: #define __GNUC__ {{.*}} +// XTENSA: #define __GXX_ABI_VERSION {{.*}} +// XTENSA: #define __ILP32__ 1 +// XTENSA: #define __INT16_C_SUFFIX__ +// XTENSA: #define __INT16_MAX__ 32767 +// XTENSA: #define __INT16_TYPE__ short +// XTENSA: #define __INT32_C_SUFFIX__ +// XTENSA: #define __INT32_MAX__ 2147483647 +// XTENSA: #define __INT32_TYPE__ int +// XTENSA: #define __INT64_C_SUFFIX__ LL +// XTENSA: #define __INT64_MAX__ 9223372036854775807LL +// XTENSA: #define __INT64_TYPE__ long long int +// XTENSA: #define __INT8_C_SUFFIX__ +// XTENSA: #define __INT8_MAX__ 127 +// XTENSA: #define __INT8_TYPE__ signed char +// XTENSA: #define __INTMAX_C_SUFFIX__ LL +// XTENSA: #define __INTMAX_MAX__ 9223372036854775807LL +// XTENSA: #define __INTMAX_TYPE__ long long int +// XTENSA: #define __INTMAX_WIDTH__ 64 +// XTENSA: #define __INTPTR_MAX__ 2147483647 +// XTENSA: #define __INTPTR_TYPE__ int +// XTENSA: #define __INTPTR_WIDTH__ 32 +// TODO: Xtensa GCC defines INT_FAST16 as int +// XTENSA: #define __INT_FAST16_MAX__ 32767 +// XTENSA: #define __INT_FAST16_TYPE__ short +// XTENSA: #define __INT_FAST16_WIDTH__ 16 +// XTENSA: #define __INT_FAST32_MAX__ 2147483647 +// XTENSA: #define __INT_FAST32_TYPE__ int +// XTENSA: #define __INT_FAST32_WIDTH__ 32 +// XTENSA: #define __INT_FAST64_MAX__ 9223372036854775807LL +// XTENSA: #define __INT_FAST64_TYPE__ long long int +// XTENSA: #define __INT_FAST64_WIDTH__ 64 +// TODO: Xtensa GCC defines INT_FAST8 as int +// XTENSA: #define __INT_FAST8_MAX__ 127 +// XTENSA: #define __INT_FAST8_TYPE__ signed char +// XTENSA: #define __INT_FAST8_WIDTH__ 8 +// XTENSA: #define __INT_LEAST16_MAX__ 32767 +// XTENSA: #define __INT_LEAST16_TYPE__ short +// XTENSA: #define __INT_LEAST16_WIDTH__ 16 +// XTENSA: #define __INT_LEAST32_MAX__ 2147483647 +// XTENSA: #define __INT_LEAST32_TYPE__ int +// XTENSA: #define __INT_LEAST32_WIDTH__ 32 +// XTENSA: #define __INT_LEAST64_MAX__ 9223372036854775807LL +// XTENSA: #define __INT_LEAST64_TYPE__ long long int +// XTENSA: #define __INT_LEAST64_WIDTH__ 64 +// XTENSA: #define __INT_LEAST8_MAX__ 127 +// XTENSA: #define __INT_LEAST8_TYPE__ signed char +// XTENSA: #define __INT_LEAST8_WIDTH__ 8 +// XTENSA: #define __INT_MAX__ 2147483647 +// XTENSA: #define __INT_WIDTH__ 32 +// XTENSA: #define __LDBL_DECIMAL_DIG__ 17 +// XTENSA: #define __LDBL_DENORM_MIN__ 4.9406564584124654e-324L +// XTENSA: #define __LDBL_DIG__ 15 +// XTENSA: #define __LDBL_EPSILON__ 2.2204460492503131e-16L +// XTENSA: #define __LDBL_HAS_DENORM__ 1 +// XTENSA: #define __LDBL_HAS_INFINITY__ 1 +// XTENSA: #define __LDBL_HAS_QUIET_NAN__ 1 +// XTENSA: #define __LDBL_MANT_DIG__ 53 +// XTENSA: #define __LDBL_MAX_10_EXP__ 308 +// XTENSA: #define __LDBL_MAX_EXP__ 1024 +// XTENSA: #define __LDBL_MAX__ 1.7976931348623157e+308L +// XTENSA: #define __LDBL_MIN_10_EXP__ (-307) +// XTENSA: #define __LDBL_MIN_EXP__ (-1021) +// XTENSA: #define __LDBL_MIN__ 2.2250738585072014e-308L +// XTENSA: #define __LDBL_NORM_MAX__ 1.7976931348623157e+308L +// XTENSA: #define __LITTLE_ENDIAN__ 1 +// XTENSA: #define __LLONG_WIDTH__ 64 +// XTENSA: #define __LONG_LONG_MAX__ 9223372036854775807LL +// XTENSA: #define __LONG_MAX__ 2147483647L +// XTENSA: #define __LONG_WIDTH__ 32 +// XTENSA: #define __MEMORY_SCOPE_DEVICE 1 +// XTENSA: #define __MEMORY_SCOPE_SINGLE 4 +// XTENSA: #define __MEMORY_SCOPE_SYSTEM 0 +// XTENSA: #define __MEMORY_SCOPE_WRKGRP 2 +// XTENSA: #define __MEMORY_SCOPE_WVFRNT 3 +// XTENSA: #define __NO_INLINE__ 1 +// XTENSA: #define __NO_MATH_ERRNO__ 1 +// XTENSA: #define __OBJC_BOOL_IS_BOOL 0 +// XTENSA: #define __POINTER_WIDTH__ 32 +// XTENSA: #define __PRAGMA_REDEFINE_EXTNAME 1 +// XTENSA: #define __PTRDIFF_MAX__ 2147483647 +// XTENSA: #define __PTRDIFF_TYPE__ int +// XTENSA: #define __PTRDIFF_WIDT... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/118008 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
