https://github.com/tclin914 updated https://github.com/llvm/llvm-project/pull/116907
>From 08523139b789c836b22677f8e16b79910de601e4 Mon Sep 17 00:00:00 2001 From: Jim Lin <j...@andestech.com> Date: Wed, 20 Nov 2024 10:31:58 +0800 Subject: [PATCH 1/3] [RISCV] Make A implies Zaamo and Zalrsc Ref: https://github.com/riscv/riscv-isa-manual/blob/main/src/a-st-ext.adoc. --- .../CodeGen/RISCV/riscv-func-attr-target.c | 20 +++++----- lld/test/ELF/lto/riscv-attributes.ll | 6 +-- lld/test/ELF/riscv-attributes.s | 16 ++++---- llvm/lib/Target/RISCV/RISCVFeatures.td | 39 ++++++++++--------- llvm/test/CodeGen/RISCV/attributes.ll | 20 +++++----- llvm/test/MC/RISCV/attribute-arch.s | 14 +++---- llvm/test/MC/RISCV/attribute.s | 4 +- 7 files changed, 60 insertions(+), 59 deletions(-) diff --git a/clang/test/CodeGen/RISCV/riscv-func-attr-target.c b/clang/test/CodeGen/RISCV/riscv-func-attr-target.c index aeddbc4ebf6895..3e9c1d9229a66b 100644 --- a/clang/test/CodeGen/RISCV/riscv-func-attr-target.c +++ b/clang/test/CodeGen/RISCV/riscv-func-attr-target.c @@ -66,16 +66,16 @@ void test_rvv_f64_type_w_zve64d() { } //. -// CHECK: attributes #0 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zifencei,+zmmul,-relax,-zbb,-zfa" } -// CHECK: attributes #1 = { {{.*}}"target-cpu"="rocket-rv64" "target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zbb,-zfa" "tune-cpu"="generic-rv64" } -// CHECK: attributes #2 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei,+zmmul,-relax,-zfa" } -// CHECK: attributes #3 = { {{.*}}"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zbb,+zicond,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zfa" } +// CHECK: attributes #0 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zaamo,+zalrsc,+zifencei,+zmmul,-relax,-zbb,-zfa" } +// CHECK: attributes #1 = { {{.*}}"target-cpu"="rocket-rv64" "target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zbb,-zfa" "tune-cpu"="generic-rv64" } +// CHECK: attributes #2 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zaamo,+zalrsc,+zbb,+zifencei,+zmmul,-relax,-zfa" } +// CHECK: attributes #3 = { {{.*}}"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zaamo,+zalrsc,+zbb,+zicond,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zfa" } // Make sure we append negative features if we override the arch -// CHECK: attributes #4 = { {{.*}}"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zbb,+zicsr,+zifencei,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" } +// CHECK: attributes #4 = { {{.*}}"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zaamo,+zalrsc,+zbb,+zicsr,+zifencei,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" } // CHECK: attributes #5 = { {{.*}}"target-features"="+64bit,+m,+save-restore,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" } -// CHECK: attributes #6 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+m,+save-restore,+zbb,+zifencei,+zmmul,-relax,-zfa" } +// CHECK: attributes #6 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+m,+save-restore,+zaamo,+zalrsc,+zbb,+zifencei,+zmmul,-relax,-zfa" } // CHECK: attributes #7 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+m,+save-restore,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" } -// CHECK: attributes #8 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zicsr,+zifencei,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" } -// CHECK: attributes #9 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zicsr,+zifencei,+zmmul,+zve32x,+zvl32b,-relax,-zbb,-zfa" } -// CHECK: attributes #11 = { {{.*}}"target-features"="+64bit,+a,+f,+m,+save-restore,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zvl32b,-relax,-zbb,-zfa" } -// CHECK: attributes #12 = { {{.*}}"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b,-relax,-zbb,-zfa" } +// CHECK: attributes #8 = { {{.*}}"target-cpu"="sifive-u54" "target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}" } +// CHECK: attributes #9 = { {{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,+zve32x,+zvl32b,-relax,-zbb,-zfa" } +// CHECK: attributes #11 = { {{.*}}"target-features"="+64bit,+a,+f,+m,+save-restore,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zvl32b,-relax,-zbb,-zfa" } +// CHECK: attributes #12 = { {{.*}}"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b,-relax,-zbb,-zfa" } diff --git a/lld/test/ELF/lto/riscv-attributes.ll b/lld/test/ELF/lto/riscv-attributes.ll index 08d8ad43dd71e6..b6d4ec820f951c 100644 --- a/lld/test/ELF/lto/riscv-attributes.ll +++ b/lld/test/ELF/lto/riscv-attributes.ll @@ -10,10 +10,10 @@ ; CHECK: BuildAttributes { ; CHECK-NEXT: FormatVersion: 0x41 ; CHECK-NEXT: Section 1 { -; CHECK-NEXT: SectionLength: 79 +; CHECK-NEXT: SectionLength: 98 ; CHECK-NEXT: Vendor: riscv ; CHECK-NEXT: Tag: Tag_File (0x1) -; CHECK-NEXT: Size: 69 +; CHECK-NEXT: Size: 88 ; CHECK-NEXT: FileAttributes { ; CHECK-NEXT: Attribute { ; CHECK-NEXT: Tag: 4 @@ -30,7 +30,7 @@ ; CHECK-NEXT: Attribute { ; CHECK-NEXT: Tag: 5 ; CHECK-NEXT: TagName: arch -; CHECK-NEXT: Value: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zmmul1p0_zbb1p0{{$}} +; CHECK-NEXT: Value: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zbb1p0{{$}} ; CHECK-NEXT: } ; CHECK-NEXT: } ; CHECK-NEXT: } diff --git a/lld/test/ELF/riscv-attributes.s b/lld/test/ELF/riscv-attributes.s index 057223c18418e1..d003a298101cbe 100644 --- a/lld/test/ELF/riscv-attributes.s +++ b/lld/test/ELF/riscv-attributes.s @@ -104,20 +104,20 @@ # UNKNOWN22: warning: unknown22a.o:(.riscv.attributes): invalid tag 0x16 at offset 0x10 # HDR: Name Type Address Off Size ES Flg Lk Inf Al -# HDR: .riscv.attributes RISCV_ATTRIBUTES 0000000000000000 000158 000047 00 0 0 1{{$}} +# HDR: .riscv.attributes RISCV_ATTRIBUTES 0000000000000000 000158 00005a 00 0 0 1{{$}} # HDR: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align # HDR: LOAD 0x000000 0x0000000000010000 0x0000000000010000 0x000158 0x000158 R 0x1000 # HDR-NEXT: GNU_STACK 0x000000 0x0000000000000000 0x0000000000000000 0x000000 0x000000 RW 0 -# HDR-NEXT: ATTRIBUTES 0x000158 0x0000000000000000 0x0000000000000000 0x000047 0x000047 R 0x1{{$}} +# HDR-NEXT: ATTRIBUTES 0x000158 0x0000000000000000 0x0000000000000000 0x00005a 0x00005a R 0x1{{$}} # CHECK: BuildAttributes { # CHECK-NEXT: FormatVersion: 0x41 # CHECK-NEXT: Section 1 { -# CHECK-NEXT: SectionLength: 70 +# CHECK-NEXT: SectionLength: 89 # CHECK-NEXT: Vendor: riscv # CHECK-NEXT: Tag: Tag_File (0x1) -# CHECK-NEXT: Size: 60 +# CHECK-NEXT: Size: 79 # CHECK-NEXT: FileAttributes { # CHECK-NEXT: Attribute { # CHECK-NEXT: Tag: 4 @@ -128,7 +128,7 @@ # CHECK-NEXT: Attribute { # CHECK-NEXT: Tag: 5 # CHECK-NEXT: TagName: arch -# CHECK-NEXT: Value: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zmmul1p0{{$}} +# CHECK-NEXT: Value: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zmmul1p0_zaamo1p0_zalrsc1p0{{$}} # CHECK-NEXT: } # CHECK-NEXT: } # CHECK-NEXT: } @@ -137,10 +137,10 @@ # CHECK2: BuildAttributes { # CHECK2-NEXT: FormatVersion: 0x41 # CHECK2-NEXT: Section 1 { -# CHECK2-NEXT: SectionLength: 113 +# CHECK2-NEXT: SectionLength: 132 # CHECK2-NEXT: Vendor: riscv # CHECK2-NEXT: Tag: Tag_File (0x1) -# CHECK2-NEXT: Size: 103 +# CHECK2-NEXT: Size: 122 # CHECK2-NEXT: FileAttributes { # CHECK2-NEXT: Attribute { # CHECK2-NEXT: Tag: 4 @@ -167,7 +167,7 @@ # CHECK2-NEXT: Attribute { # CHECK2-NEXT: Tag: 5 # CHECK2-NEXT: TagName: arch -# CHECK2-NEXT: Value: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zmmul1p0_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0{{$}} +# CHECK2-NEXT: Value: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0{{$}} # CHECK2-NEXT: } # CHECK2-NEXT: } # CHECK2-NEXT: } diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 3977816ebdd49c..35d9b3af9f4fdb 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -203,9 +203,28 @@ def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">, // Atomic Extensions +def FeatureStdExtZaamo + : RISCVExtension<"zaamo", 1, 0, + "'Zaamo' (Atomic Memory Operations)">; +def HasStdExtAOrZaamo + : Predicate<"Subtarget->hasStdExtZaamo()">, + AssemblerPredicate<(any_of FeatureStdExtZaamo), + "'A' (Atomic Instructions) or " + "'Zaamo' (Atomic Memory Operations)">; + +def FeatureStdExtZalrsc + : RISCVExtension<"zalrsc", 1, 0, + "'Zalrsc' (Load-Reserved/Store-Conditional)">; +def HasStdExtAOrZalrsc + : Predicate<"Subtarget->hasStdExtZalrsc()">, + AssemblerPredicate<(any_of FeatureStdExtZalrsc), + "'A' (Atomic Instructions) or " + "'Zalrsc' (Load-Reserved/Store-Conditional)">; + def FeatureStdExtA : RISCVExtension<"a", 2, 1, - "'A' (Atomic Instructions)">, + "'A' (Atomic Instructions)", + [FeatureStdExtZaamo, FeatureStdExtZalrsc]>, RISCVExtensionBitmask<0, 0>; def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">, AssemblerPredicate<(all_of FeatureStdExtA), @@ -226,15 +245,6 @@ def FeatureStdExtZa64rs : RISCVExtension<"za64rs", 1, 0, def FeatureStdExtZa128rs : RISCVExtension<"za128rs", 1, 0, "'Za128rs' (Reservation Set Size of at Most 128 Bytes)">; -def FeatureStdExtZaamo - : RISCVExtension<"zaamo", 1, 0, - "'Zaamo' (Atomic Memory Operations)">; -def HasStdExtAOrZaamo - : Predicate<"Subtarget->hasStdExtA() || Subtarget->hasStdExtZaamo()">, - AssemblerPredicate<(any_of FeatureStdExtA, FeatureStdExtZaamo), - "'A' (Atomic Instructions) or " - "'Zaamo' (Atomic Memory Operations)">; - def FeatureStdExtZabha : RISCVExtension<"zabha", 1, 0, "'Zabha' (Byte and Halfword Atomic Memory Operations)", @@ -260,15 +270,6 @@ def HasStdExtZalasr : Predicate<"Subtarget->hasStdExtZalasr()">, AssemblerPredicate<(all_of FeatureStdExtZalasr), "'Zalasr' (Load-Acquire and Store-Release Instructions)">; -def FeatureStdExtZalrsc - : RISCVExtension<"zalrsc", 1, 0, - "'Zalrsc' (Load-Reserved/Store-Conditional)">; -def HasStdExtAOrZalrsc - : Predicate<"Subtarget->hasStdExtA() || Subtarget->hasStdExtZalrsc()">, - AssemblerPredicate<(any_of FeatureStdExtA, FeatureStdExtZalrsc), - "'A' (Atomic Instructions) or " - "'Zalrsc' (Load-Reserved/Store-Conditional)">; - def FeatureStdExtZama16b : RISCVExtension<"zama16b", 1, 0, "'Zama16b' (Atomic 16-byte misaligned loads, stores and AMOs)">; diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 1c8c459d1b316e..b47b5ec460a7c3 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -306,7 +306,7 @@ ; RV32M: .attribute 5, "rv32i2p1_m2p0_zmmul1p0" ; RV32ZMMUL: .attribute 5, "rv32i2p1_zmmul1p0" ; RV32MZMMUL: .attribute 5, "rv32i2p1_m2p0_zmmul1p0" -; RV32A: .attribute 5, "rv32i2p1_a2p1" +; RV32A: .attribute 5, "rv32i2p1_a2p1_zaamo1p0_zalrsc1p0" ; RV32B: .attribute 5, "rv32i2p1_b1p0_zba1p0_zbb1p0_zbs1p0" ; RV32F: .attribute 5, "rv32i2p1_f2p2_zicsr2p0" ; RV32D: .attribute 5, "rv32i2p1_f2p2_d2p2_zicsr2p0" @@ -446,7 +446,7 @@ ; RV64M: .attribute 5, "rv64i2p1_m2p0_zmmul1p0" ; RV64ZMMUL: .attribute 5, "rv64i2p1_zmmul1p0" ; RV64MZMMUL: .attribute 5, "rv64i2p1_m2p0_zmmul1p0" -; RV64A: .attribute 5, "rv64i2p1_a2p1" +; RV64A: .attribute 5, "rv64i2p1_a2p1_zaamo1p0_zalrsc1p0" ; RV64B: .attribute 5, "rv64i2p1_b1p0_zba1p0_zbb1p0_zbs1p0" ; RV64F: .attribute 5, "rv64i2p1_f2p2_zicsr2p0" ; RV64D: .attribute 5, "rv64i2p1_f2p2_d2p2_zicsr2p0" @@ -590,14 +590,14 @@ ; RVI20U32: .attribute 5, "rv32i2p1" ; RVI20U64: .attribute 5, "rv64i2p1" -; RVA20U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zmmul1p0_za128rs1p0" -; RVA20S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zifencei2p0_zmmul1p0_za128rs1p0_ssccptr1p0_sstvala1p0_sstvecd1p0_svade1p0_svbare1p0" -; RVA22U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zihintpause2p0_zihpm2p0_zmmul1p0_za64rs1p0_zfhmin1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0" -; RVA22S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zifencei2p0_zihintpause2p0_zihpm2p0_zmmul1p0_za64rs1p0_zfhmin1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_ssccptr1p0_sscounterenw1p0_sstvala1p0_sstvecd1p0_svade1p0_svbare1p0_svinval1p0_svpbmt1p0" -; RVA23U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_supm1p0" -; RVA23S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_v1p0_h1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_sha1p0_shcounterenw1p0_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_ssnpm1p0_ssstateen1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_supm1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0" -; RVB23U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zawrs1p0_zfa1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0" -; RVB23S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zawrs1p0_zfa1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0" +; RVA20U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zmmul1p0_za128rs1p0_zaamo1p0_zalrsc1p0" +; RVA20S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zifencei2p0_zmmul1p0_za128rs1p0_zaamo1p0_zalrsc1p0_ssccptr1p0_sstvala1p0_sstvecd1p0_svade1p0_svbare1p0" +; RVA22U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zihintpause2p0_zihpm2p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zfhmin1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0" +; RVA22S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zifencei2p0_zihintpause2p0_zihpm2p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zfhmin1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_ssccptr1p0_sscounterenw1p0_sstvala1p0_sstvecd1p0_svade1p0_svbare1p0_svinval1p0_svpbmt1p0" +; RVA23U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_supm1p0" +; RVA23S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_v1p0_h1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_sha1p0_shcounterenw1p0_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_ssnpm1p0_ssstateen1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_supm1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0" +; RVB23U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0" +; RVB23S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0" ; RVM23U32: .attribute 5, "rv32i2p1_m2p0_b1p0_zicbop1p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zimop1p0_zmmul1p0_zca1p0_zcb1p0_zce1p0_zcmop1p0_zcmp1p0_zcmt1p0_zba1p0_zbb1p0_zbs1p0" define i32 @addi(i32 %a) { diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index 30cf037b1f70a4..9cb4387c720b3b 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -20,22 +20,22 @@ # CHECK: attribute 5, "rv32i2p1_m2p0_zmmul1p0" .attribute arch, "rv32i2p1_ma" -# CHECK: attribute 5, "rv32i2p1_m2p0_a2p1_zmmul1p0" +# CHECK: attribute 5, "rv32i2p1_m2p0_a2p1_zmmul1p0_zaamo1p0_zalrsc1p0" .attribute arch, "rv32g" -# CHECK: attribute 5, "rv32i2p1_m2p0_a2p1_f2p2_d2p2_zicsr2p0_zifencei2p0_zmmul1p0" +# CHECK: attribute 5, "rv32i2p1_m2p0_a2p1_f2p2_d2p2_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0" .attribute arch, "rv32imafdc" -# CHECK: attribute 5, "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zmmul1p0" +# CHECK: attribute 5, "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zmmul1p0_zaamo1p0_zalrsc1p0" .attribute arch, "rv32i2p1_mafdc" -# CHECK: attribute 5, "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zmmul1p0" +# CHECK: attribute 5, "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zmmul1p0_zaamo1p0_zalrsc1p0" .attribute arch, "rv32ima2p1_fdc" -# CHECK: attribute 5, "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zmmul1p0" +# CHECK: attribute 5, "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zmmul1p0_zaamo1p0_zalrsc1p0" .attribute arch, "rv32ima2p1_fdc" -# CHECK: attribute 5, "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zmmul1p0" +# CHECK: attribute 5, "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zmmul1p0_zaamo1p0_zalrsc1p0" .attribute arch, "rv32iv" # CHECK: attribute 5, "rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" @@ -394,7 +394,7 @@ # CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0" .attribute arch, "rv32ia_zacas1p0" -# CHECK: attribute 5, "rv32i2p1_a2p1_zaamo1p0_zacas1p0" +# CHECK: attribute 5, "rv32i2p1_a2p1_zaamo1p0_zacas1p0_zalrsc1p0" .attribute arch, "rv32izalasr0p1" # CHECK: attribute 5, "rv32i2p1_zalasr0p1" diff --git a/llvm/test/MC/RISCV/attribute.s b/llvm/test/MC/RISCV/attribute.s index 29a450071fccd0..2763db2c2a45d6 100644 --- a/llvm/test/MC/RISCV/attribute.s +++ b/llvm/test/MC/RISCV/attribute.s @@ -10,8 +10,8 @@ .attribute stack_align, 16 # CHECK: attribute 4, 16 -.attribute arch, "rv32i2p1_m2p0_a2p1_c2p0_zmmul1p0" -# CHECK: attribute 5, "rv32i2p1_m2p0_a2p1_c2p0_zmmul1p0" +.attribute arch, "rv32i2p1_m2p0_a2p1_c2p0_zmmul1p0_zaamo1p0_zalrsc1p0" +# CHECK: attribute 5, "rv32i2p1_m2p0_a2p1_c2p0_zmmul1p0_zaamo1p0_zalrsc1p0" .attribute unaligned_access, 0 # CHECK: attribute 6, 0 >From c96306793003a60bd9a2ba37eadd4dd107169b65 Mon Sep 17 00:00:00 2001 From: Jim Tsung-Chun Lin <j...@andestech.com> Date: Thu, 21 Nov 2024 13:20:46 +0800 Subject: [PATCH 2/3] Update llvm unit test --- .../TargetParser/RISCVISAInfoTest.cpp | 32 ++++++++++++++----- 1 file changed, 24 insertions(+), 8 deletions(-) diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index 2312fe9df81420..5ce16db39e8b51 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -223,7 +223,7 @@ TEST(ParseArchString, AcceptsSupportedBaseISAsAndSetsXLenAndFLen) { ASSERT_THAT_EXPECTED(MaybeRV32G, Succeeded()); RISCVISAInfo &InfoRV32G = **MaybeRV32G; const auto &ExtsRV32G = InfoRV32G.getExtensions(); - EXPECT_EQ(ExtsRV32G.size(), 8UL); + EXPECT_EQ(ExtsRV32G.size(), 10UL); EXPECT_TRUE(ExtsRV32G.at("i") == (RISCVISAUtils::ExtensionVersion{2, 1})); EXPECT_TRUE(ExtsRV32G.at("m") == (RISCVISAUtils::ExtensionVersion{2, 0})); EXPECT_TRUE(ExtsRV32G.at("a") == (RISCVISAUtils::ExtensionVersion{2, 1})); @@ -233,6 +233,8 @@ TEST(ParseArchString, AcceptsSupportedBaseISAsAndSetsXLenAndFLen) { EXPECT_TRUE(ExtsRV32G.at("zifencei") == (RISCVISAUtils::ExtensionVersion{2, 0})); EXPECT_TRUE(ExtsRV32G.at("zmmul") == (RISCVISAUtils::ExtensionVersion{1, 0})); + EXPECT_TRUE(ExtsRV32G.at("zaamo") == (RISCVISAUtils::ExtensionVersion{1, 0})); + EXPECT_TRUE(ExtsRV32G.at("zalrsc") == (RISCVISAUtils::ExtensionVersion{1, 0})); EXPECT_EQ(InfoRV32G.getXLen(), 32U); EXPECT_EQ(InfoRV32G.getFLen(), 64U); EXPECT_EQ(InfoRV32G.getMinVLen(), 0U); @@ -267,7 +269,7 @@ TEST(ParseArchString, AcceptsSupportedBaseISAsAndSetsXLenAndFLen) { ASSERT_THAT_EXPECTED(MaybeRV64G, Succeeded()); RISCVISAInfo &InfoRV64G = **MaybeRV64G; const auto &ExtsRV64G = InfoRV64G.getExtensions(); - EXPECT_EQ(ExtsRV64G.size(), 8UL); + EXPECT_EQ(ExtsRV64G.size(), 10UL); EXPECT_TRUE(ExtsRV64G.at("i") == (RISCVISAUtils::ExtensionVersion{2, 1})); EXPECT_TRUE(ExtsRV64G.at("m") == (RISCVISAUtils::ExtensionVersion{2, 0})); EXPECT_TRUE(ExtsRV64G.at("a") == (RISCVISAUtils::ExtensionVersion{2, 1})); @@ -277,6 +279,8 @@ TEST(ParseArchString, AcceptsSupportedBaseISAsAndSetsXLenAndFLen) { EXPECT_TRUE(ExtsRV64G.at("zifencei") == (RISCVISAUtils::ExtensionVersion{2, 0})); EXPECT_TRUE(ExtsRV64G.at("zmmul") == (RISCVISAUtils::ExtensionVersion{1, 0})); + EXPECT_TRUE(ExtsRV64G.at("zaamo") == (RISCVISAUtils::ExtensionVersion{1, 0})); + EXPECT_TRUE(ExtsRV64G.at("zalrsc") == (RISCVISAUtils::ExtensionVersion{1, 0})); EXPECT_EQ(InfoRV64G.getXLen(), 64U); EXPECT_EQ(InfoRV64G.getFLen(), 64U); EXPECT_EQ(InfoRV64G.getMinVLen(), 0U); @@ -287,7 +291,7 @@ TEST(ParseArchString, AcceptsSupportedBaseISAsAndSetsXLenAndFLen) { ASSERT_THAT_EXPECTED(MaybeRV64GCV, Succeeded()); RISCVISAInfo &InfoRV64GCV = **MaybeRV64GCV; const auto &ExtsRV64GCV = InfoRV64GCV.getExtensions(); - EXPECT_EQ(ExtsRV64GCV.size(), 18UL); + EXPECT_EQ(ExtsRV64GCV.size(), 20UL); EXPECT_TRUE(ExtsRV64GCV.at("i") == (RISCVISAUtils::ExtensionVersion{2, 1})); EXPECT_TRUE(ExtsRV64GCV.at("m") == (RISCVISAUtils::ExtensionVersion{2, 0})); EXPECT_TRUE(ExtsRV64GCV.at("a") == (RISCVISAUtils::ExtensionVersion{2, 1})); @@ -298,6 +302,8 @@ TEST(ParseArchString, AcceptsSupportedBaseISAsAndSetsXLenAndFLen) { EXPECT_TRUE(ExtsRV64GCV.at("zifencei") == (RISCVISAUtils::ExtensionVersion{2, 0})); EXPECT_TRUE(ExtsRV64G.at("zmmul") == (RISCVISAUtils::ExtensionVersion{1, 0})); + EXPECT_TRUE(ExtsRV64G.at("zaamo") == (RISCVISAUtils::ExtensionVersion{1, 0})); + EXPECT_TRUE(ExtsRV64G.at("zalrsc") == (RISCVISAUtils::ExtensionVersion{1, 0})); EXPECT_TRUE(ExtsRV64GCV.at("v") == (RISCVISAUtils::ExtensionVersion{1, 0})); EXPECT_TRUE(ExtsRV64GCV.at("zve32x") == (RISCVISAUtils::ExtensionVersion{1, 0})); EXPECT_TRUE(ExtsRV64GCV.at("zve32f") == (RISCVISAUtils::ExtensionVersion{1, 0})); @@ -379,7 +385,7 @@ TEST(ParseArchString, AcceptsUnderscoreSplittingExtensions) { auto MaybeISAInfo = RISCVISAInfo::parseArchString(Input, true); ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded()); const auto &Exts = (*MaybeISAInfo)->getExtensions(); - EXPECT_EQ(Exts.size(), 9UL); + EXPECT_EQ(Exts.size(), 11UL); EXPECT_EQ(Exts.count("i"), 1U); EXPECT_EQ(Exts.count("m"), 1U); EXPECT_EQ(Exts.count("a"), 1U); @@ -389,6 +395,8 @@ TEST(ParseArchString, AcceptsUnderscoreSplittingExtensions) { EXPECT_EQ(Exts.count("zicsr"), 1U); EXPECT_EQ(Exts.count("zifencei"), 1U); EXPECT_EQ(Exts.count("zmmul"), 1U); + EXPECT_EQ(Exts.count("zaamo"), 1U); + EXPECT_EQ(Exts.count("zalrsc"), 1U); } } @@ -398,7 +406,7 @@ TEST(ParseArchString, AcceptsRelaxSingleLetterExtensions) { auto MaybeISAInfo = RISCVISAInfo::parseArchString(Input, true); ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded()); const auto &Exts = (*MaybeISAInfo)->getExtensions(); - EXPECT_EQ(Exts.size(), 7UL); + EXPECT_EQ(Exts.size(), 9UL); EXPECT_EQ(Exts.count("i"), 1U); EXPECT_EQ(Exts.count("m"), 1U); EXPECT_EQ(Exts.count("f"), 1U); @@ -406,6 +414,8 @@ TEST(ParseArchString, AcceptsRelaxSingleLetterExtensions) { EXPECT_EQ(Exts.count("d"), 1U); EXPECT_EQ(Exts.count("zicsr"), 1U); EXPECT_EQ(Exts.count("zmmul"), 1U); + EXPECT_EQ(Exts.count("zaamo"), 1U); + EXPECT_EQ(Exts.count("zalrsc"), 1U); } } @@ -416,7 +426,7 @@ TEST(ParseArchString, AcceptsRelaxMixedLetterExtensions) { auto MaybeISAInfo = RISCVISAInfo::parseArchString(Input, true); ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded()); const auto &Exts = (*MaybeISAInfo)->getExtensions(); - EXPECT_EQ(Exts.size(), 9UL); + EXPECT_EQ(Exts.size(), 11UL); EXPECT_EQ(Exts.count("i"), 1U); EXPECT_EQ(Exts.count("m"), 1U); EXPECT_EQ(Exts.count("a"), 1U); @@ -426,6 +436,8 @@ TEST(ParseArchString, AcceptsRelaxMixedLetterExtensions) { EXPECT_EQ(Exts.count("svinval"), 1U); EXPECT_EQ(Exts.count("zicsr"), 1U); EXPECT_EQ(Exts.count("zmmul"), 1U); + EXPECT_EQ(Exts.count("zaamo"), 1U); + EXPECT_EQ(Exts.count("zalrsc"), 1U); } } @@ -445,12 +457,14 @@ TEST(ParseArchString, AcceptsAmbiguousFromRelaxExtensions) { auto MaybeISAInfo = RISCVISAInfo::parseArchString(Input, true); ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded()); const auto &Exts = (*MaybeISAInfo)->getExtensions(); - EXPECT_EQ(Exts.size(), 5UL); + EXPECT_EQ(Exts.size(), 7UL); EXPECT_EQ(Exts.count("i"), 1U); EXPECT_EQ(Exts.count("zba"), 1U); EXPECT_EQ(Exts.count("m"), 1U); EXPECT_EQ(Exts.count("a"), 1U); EXPECT_EQ(Exts.count("zmmul"), 1U); + EXPECT_EQ(Exts.count("zaamo"), 1U); + EXPECT_EQ(Exts.count("zalrsc"), 1U); } } @@ -681,7 +695,7 @@ TEST(ParseArchString, AcceptsBareProfileNames) { auto MaybeRVA20U64 = RISCVISAInfo::parseArchString("rva20u64", true); ASSERT_THAT_EXPECTED(MaybeRVA20U64, Succeeded()); const auto &Exts = (*MaybeRVA20U64)->getExtensions(); - EXPECT_EQ(Exts.size(), 14UL); + EXPECT_EQ(Exts.size(), 16UL); EXPECT_EQ(Exts.count("i"), 1U); EXPECT_EQ(Exts.count("m"), 1U); EXPECT_EQ(Exts.count("f"), 1U); @@ -696,6 +710,8 @@ TEST(ParseArchString, AcceptsBareProfileNames) { EXPECT_EQ(Exts.count("ziccamoa"), 1U); EXPECT_EQ(Exts.count("zicclsm"), 1U); EXPECT_EQ(Exts.count("zmmul"), 1U); + EXPECT_EQ(Exts.count("zaamo"), 1U); + EXPECT_EQ(Exts.count("zalrsc"), 1U); auto MaybeRVA23U64 = RISCVISAInfo::parseArchString("rva23u64", true); ASSERT_THAT_EXPECTED(MaybeRVA23U64, Succeeded()); >From bf51e7704ccdda72743080e9b36650e37ea10f47 Mon Sep 17 00:00:00 2001 From: Jim Tsung-Chun Lin <j...@andestech.com> Date: Thu, 21 Nov 2024 13:22:02 +0800 Subject: [PATCH 3/3] Update the names and description in RISCVFeatures.td --- llvm/lib/Target/RISCV/RISCVFeatures.td | 6 ++---- llvm/lib/Target/RISCV/RISCVInstrInfoA.td | 16 ++++++++-------- llvm/test/MC/RISCV/rv32i-invalid.s | 4 ++-- 3 files changed, 12 insertions(+), 14 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 35d9b3af9f4fdb..140185ab909e8e 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -206,19 +206,17 @@ def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">, def FeatureStdExtZaamo : RISCVExtension<"zaamo", 1, 0, "'Zaamo' (Atomic Memory Operations)">; -def HasStdExtAOrZaamo +def HasStdExtZaamo : Predicate<"Subtarget->hasStdExtZaamo()">, AssemblerPredicate<(any_of FeatureStdExtZaamo), - "'A' (Atomic Instructions) or " "'Zaamo' (Atomic Memory Operations)">; def FeatureStdExtZalrsc : RISCVExtension<"zalrsc", 1, 0, "'Zalrsc' (Load-Reserved/Store-Conditional)">; -def HasStdExtAOrZalrsc +def HasStdExtZalrsc : Predicate<"Subtarget->hasStdExtZalrsc()">, AssemblerPredicate<(any_of FeatureStdExtZalrsc), - "'A' (Atomic Instructions) or " "'Zalrsc' (Load-Reserved/Store-Conditional)">; def FeatureStdExtA diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td index 10e919c902d518..9685d85864ebbc 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td @@ -60,13 +60,13 @@ multiclass AMO_rr_aq_rl<bits<5> funct5, bits<3> funct3, string opcodestr> { // Instructions //===----------------------------------------------------------------------===// -let Predicates = [HasStdExtAOrZalrsc], IsSignExtendingOpW = 1 in { +let Predicates = [HasStdExtZalrsc], IsSignExtendingOpW = 1 in { defm LR_W : LR_r_aq_rl<0b010, "lr.w">, Sched<[WriteAtomicLDW, ReadAtomicLDW]>; defm SC_W : SC_r_aq_rl<0b010, "sc.w">, Sched<[WriteAtomicSTW, ReadAtomicSTW, ReadAtomicSTW]>; -} // Predicates = [HasStdExtAOrZalrsc], IsSignExtendingOpW = 1 +} // Predicates = [HasStdExtZalrsc], IsSignExtendingOpW = 1 -let Predicates = [HasStdExtAOrZaamo], IsSignExtendingOpW = 1 in { +let Predicates = [HasStdExtZaamo], IsSignExtendingOpW = 1 in { defm AMOSWAP_W : AMO_rr_aq_rl<0b00001, 0b010, "amoswap.w">, Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>; defm AMOADD_W : AMO_rr_aq_rl<0b00000, 0b010, "amoadd.w">, @@ -85,15 +85,15 @@ defm AMOMINU_W : AMO_rr_aq_rl<0b11000, 0b010, "amominu.w">, Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>; defm AMOMAXU_W : AMO_rr_aq_rl<0b11100, 0b010, "amomaxu.w">, Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>; -} // Predicates = [HasStdExtAOrZaamo], IsSignExtendingOpW = 1 +} // Predicates = [HasStdExtZaamo], IsSignExtendingOpW = 1 -let Predicates = [HasStdExtAOrZalrsc, IsRV64] in { +let Predicates = [HasStdExtZalrsc, IsRV64] in { defm LR_D : LR_r_aq_rl<0b011, "lr.d">, Sched<[WriteAtomicLDD, ReadAtomicLDD]>; defm SC_D : SC_r_aq_rl<0b011, "sc.d">, Sched<[WriteAtomicSTD, ReadAtomicSTD, ReadAtomicSTD]>; -} // Predicates = [HasStdExtAOrZalrsc, IsRV64] +} // Predicates = [HasStdExtZalrsc, IsRV64] -let Predicates = [HasStdExtAOrZaamo, IsRV64] in { +let Predicates = [HasStdExtZaamo, IsRV64] in { defm AMOSWAP_D : AMO_rr_aq_rl<0b00001, 0b011, "amoswap.d">, Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>; defm AMOADD_D : AMO_rr_aq_rl<0b00000, 0b011, "amoadd.d">, @@ -112,7 +112,7 @@ defm AMOMINU_D : AMO_rr_aq_rl<0b11000, 0b011, "amominu.d">, Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>; defm AMOMAXU_D : AMO_rr_aq_rl<0b11100, 0b011, "amomaxu.d">, Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>; -} // Predicates = [HasStdExtAOrZaamo, IsRV64] +} // Predicates = [HasStdExtZaamo, IsRV64] //===----------------------------------------------------------------------===// // Pseudo-instructions and codegen patterns diff --git a/llvm/test/MC/RISCV/rv32i-invalid.s b/llvm/test/MC/RISCV/rv32i-invalid.s index e0e1e4241ec987..ac0e3c6c1bdbfe 100644 --- a/llvm/test/MC/RISCV/rv32i-invalid.s +++ b/llvm/test/MC/RISCV/rv32i-invalid.s @@ -183,8 +183,8 @@ xor s2, s2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction # Instruction not in the base ISA div a4, ra, s0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'M' (Integer Multiplication and Division){{$}} -amomaxu.w s5, s4, (s3) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'A' (Atomic Instructions) or 'Zaamo' (Atomic Memory Operations){{$}} -lr.w t0, (t1) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'A' (Atomic Instructions) or 'Zalrsc' (Load-Reserved/Store-Conditional){{$}} +amomaxu.w s5, s4, (s3) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zaamo' (Atomic Memory Operations){{$}} +lr.w t0, (t1) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zalrsc' (Load-Reserved/Store-Conditional){{$}} fadd.s ft0, ft1, ft2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point){{$}} fadd.h ft0, ft1, ft2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point){{$}} fadd.s a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfinx' (Float in Integer){{$}} _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
