llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-clang Author: Joseph Huber (jhuber6) <details> <summary>Changes</summary> Summary: The cache line size on AMDGPU varies between 64 and 128 (The lowest L2 cache also goes to 256 on some architectures.) This macro is intended to present a size that will not cause destructive interference, so we choose the larger of those values. --- Full diff: https://github.com/llvm/llvm-project/pull/115241.diff 1 Files Affected: - (modified) clang/lib/Basic/Targets/AMDGPU.h (+4) ``````````diff diff --git a/clang/lib/Basic/Targets/AMDGPU.h b/clang/lib/Basic/Targets/AMDGPU.h index 6edd3474d4edae..81e96ed65c47bf 100644 --- a/clang/lib/Basic/Targets/AMDGPU.h +++ b/clang/lib/Basic/Targets/AMDGPU.h @@ -462,6 +462,10 @@ class LLVM_LIBRARY_VISIBILITY AMDGPUTargetInfo final : public TargetInfo { } bool hasHIPImageSupport() const override { return HasImage; } + + std::pair<unsigned, unsigned> hardwareInterferenceSizes() const override { + return std::make_pair(128, 128); + } }; } // namespace targets `````````` </details> https://github.com/llvm/llvm-project/pull/115241 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
