[clang] [llvm] [SystemZ] Add support for half (fp16) (PR #109164)

[Jonas Paulsson via cfe-commits]

================
@@ -1597,6 +1618,15 @@ bool SystemZTargetLowering::splitValueIntoRegisterParts(
     return true;
   }
 
+  // Convert f16 to f32 (Out-arg).
+  if (PartVT == MVT::f16) {
+    assert(NumParts == 1 && "");
+    SDValue I16Val = DAG.getBitcast(MVT::i16, Val);
+    SDValue I32Val = DAG.getAnyExtOrTrunc(I16Val, DL, MVT::i32);
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JonPsson1 wrote:

ops, yes, fixed.

https://github.com/llvm/llvm-project/pull/109164
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