================ @@ -2238,6 +2256,17 @@ MVT RISCVTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context, return PartVT; } +unsigned +RISCVTargetLowering::getNumRegisters(LLVMContext &Context, EVT VT, ---------------- topperc wrote:
Why did we need this change but AArch64 didn't? https://github.com/llvm/llvm-project/pull/112983 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
