llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-clang Author: Rahul Joshi (jurahul) <details> <summary>Changes</summary> Change SetTheory::RecSet/RecVec to use const Record pointers. --- Patch is 27.91 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/107692.diff 11 Files Affected: - (modified) clang/utils/TableGen/NeonEmitter.cpp (+1-1) - (modified) llvm/include/llvm/TableGen/Record.h (+3-3) - (modified) llvm/include/llvm/TableGen/SetTheory.h (+2-2) - (modified) llvm/lib/TableGen/Record.cpp (+4-6) - (modified) llvm/utils/TableGen/AsmMatcherEmitter.cpp (+20-18) - (modified) llvm/utils/TableGen/Common/CodeGenRegisters.cpp (+13-16) - (modified) llvm/utils/TableGen/Common/CodeGenRegisters.h (+9-7) - (modified) llvm/utils/TableGen/Common/CodeGenSchedule.cpp (+14-13) - (modified) llvm/utils/TableGen/Common/CodeGenSchedule.h (+6-4) - (modified) llvm/utils/TableGen/RegisterInfoEmitter.cpp (+15-15) - (modified) llvm/utils/TableGen/TableGen.cpp (+1-1) ``````````diff diff --git a/clang/utils/TableGen/NeonEmitter.cpp b/clang/utils/TableGen/NeonEmitter.cpp index e0d7b0db7f5780..4707ce1ea3b792 100644 --- a/clang/utils/TableGen/NeonEmitter.cpp +++ b/clang/utils/TableGen/NeonEmitter.cpp @@ -1636,7 +1636,7 @@ std::pair<Type, std::string> Intrinsic::DagEmitter::emitDagShuffle(DagInit *DI){ int64_t VectorSize = cast<IntInit>(Expr->getArg(0))->getValue(); VectorSize /= ElementSize; - std::vector<Record *> Revved; + std::vector<const Record *> Revved; for (unsigned VI = 0; VI < Elts2.size(); VI += VectorSize) { for (int LI = VectorSize - 1; LI >= 0; --LI) { Revved.push_back(Elts2[VI + LI]); diff --git a/llvm/include/llvm/TableGen/Record.h b/llvm/include/llvm/TableGen/Record.h index 5d36fcf57e23e3..f6c751af6bb836 100644 --- a/llvm/include/llvm/TableGen/Record.h +++ b/llvm/include/llvm/TableGen/Record.h @@ -1323,7 +1323,7 @@ class DefInit : public TypedInit { return I->getKind() == IK_DefInit; } - static DefInit *get(Record*); + static DefInit *get(const Record *); Init *convertInitializerTo(RecTy *Ty) const override; @@ -1673,7 +1673,7 @@ class Record { RecordKeeper &TrackedRecords; // The DefInit corresponding to this record. - DefInit *CorrespondingDefInit = nullptr; + mutable DefInit *CorrespondingDefInit = nullptr; // Unique record ID. unsigned ID; @@ -1740,7 +1740,7 @@ class Record { RecordRecTy *getType(); /// get the corresponding DefInit. - DefInit *getDefInit(); + DefInit *getDefInit() const; bool isClass() const { return Kind == RK_Class; } diff --git a/llvm/include/llvm/TableGen/SetTheory.h b/llvm/include/llvm/TableGen/SetTheory.h index 954453b783d4d8..771dcff2f214c3 100644 --- a/llvm/include/llvm/TableGen/SetTheory.h +++ b/llvm/include/llvm/TableGen/SetTheory.h @@ -64,8 +64,8 @@ class Record; class SetTheory { public: - using RecVec = std::vector<Record *>; - using RecSet = SmallSetVector<Record *, 16>; + using RecVec = std::vector<const Record *>; + using RecSet = SmallSetVector<const Record *, 16>; /// Operator - A callback representing a DAG operator. class Operator { diff --git a/llvm/lib/TableGen/Record.cpp b/llvm/lib/TableGen/Record.cpp index 17afa2f7eb1b99..79c5e071e55f23 100644 --- a/llvm/lib/TableGen/Record.cpp +++ b/llvm/lib/TableGen/Record.cpp @@ -2235,9 +2235,7 @@ Init *VarBitInit::resolveReferences(Resolver &R) const { DefInit::DefInit(Record *D) : TypedInit(IK_DefInit, D->getType()), Def(D) {} -DefInit *DefInit::get(Record *R) { - return R->getDefInit(); -} +DefInit *DefInit::get(const Record *R) { return R->getDefInit(); } Init *DefInit::convertInitializerTo(RecTy *Ty) const { if (auto *RRT = dyn_cast<RecordRecTy>(Ty)) @@ -2808,10 +2806,10 @@ RecordRecTy *Record::getType() { return RecordRecTy::get(TrackedRecords, DirectSCs); } -DefInit *Record::getDefInit() { +DefInit *Record::getDefInit() const { if (!CorrespondingDefInit) { - CorrespondingDefInit = - new (TrackedRecords.getImpl().Allocator) DefInit(this); + CorrespondingDefInit = new (TrackedRecords.getImpl().Allocator) + DefInit(const_cast<Record *>(this)); } return CorrespondingDefInit; } diff --git a/llvm/utils/TableGen/AsmMatcherEmitter.cpp b/llvm/utils/TableGen/AsmMatcherEmitter.cpp index f351087ad212f7..574a3344a02f8d 100644 --- a/llvm/utils/TableGen/AsmMatcherEmitter.cpp +++ b/llvm/utils/TableGen/AsmMatcherEmitter.cpp @@ -140,7 +140,7 @@ class AsmMatcherInfo; // RegisterSets can be seen in the outputted AsmMatcher tables occasionally, and // can even affect compiler output (at least seen in diagnostics produced when // all matches fail). So we use a type that sorts them consistently. -typedef std::set<Record *, LessRecordByID> RegisterSet; +typedef std::set<const Record *, LessRecordByID> RegisterSet; class AsmMatcherEmitter { RecordKeeper &Records; @@ -242,7 +242,7 @@ struct ClassInfo { if (!isRegisterClass() || !RHS.isRegisterClass()) return false; - std::vector<Record *> Tmp; + std::vector<const Record *> Tmp; std::set_intersection(Registers.begin(), Registers.end(), RHS.Registers.begin(), RHS.Registers.end(), std::back_inserter(Tmp), LessRecordByID()); @@ -403,7 +403,7 @@ struct MatchableInfo { bool IsIsolatedToken; /// Register record if this token is singleton register. - Record *SingletonReg; + const Record *SingletonReg; explicit AsmOperand(bool IsIsolatedToken, StringRef T) : Token(T), Class(nullptr), SubOpIdx(-1), @@ -582,7 +582,7 @@ struct MatchableInfo { void formTwoOperandAlias(StringRef Constraint); void initialize(const AsmMatcherInfo &Info, - SmallPtrSetImpl<Record *> &SingletonRegisters, + SmallPtrSetImpl<const Record *> &SingletonRegisters, AsmVariantInfo const &Variant, bool HasMnemonicFirst); /// validate - Return true if this matchable is a valid thing to match against @@ -757,7 +757,8 @@ class AsmMatcherInfo { std::vector<OperandMatchEntry> OperandMatchInfo; /// Map of Register records to their class information. - typedef std::map<Record *, ClassInfo *, LessRecordByID> RegisterClassesTy; + typedef std::map<const Record *, ClassInfo *, LessRecordByID> + RegisterClassesTy; RegisterClassesTy RegisterClasses; /// Map of Predicate records to their subtarget information. @@ -784,7 +785,8 @@ class AsmMatcherInfo { /// buildRegisterClasses - Build the ClassInfo* instances for register /// classes. - void buildRegisterClasses(SmallPtrSetImpl<Record *> &SingletonRegisters); + void + buildRegisterClasses(SmallPtrSetImpl<const Record *> &SingletonRegisters); /// buildOperandClasses - Build the ClassInfo* instances for user defined /// operand classes. @@ -935,10 +937,10 @@ static void extractSingletonRegisterForAsmOperand(MatchableInfo::AsmOperand &Op, // be some random non-register token, just ignore it. } -void MatchableInfo::initialize(const AsmMatcherInfo &Info, - SmallPtrSetImpl<Record *> &SingletonRegisters, - AsmVariantInfo const &Variant, - bool HasMnemonicFirst) { +void MatchableInfo::initialize( + const AsmMatcherInfo &Info, + SmallPtrSetImpl<const Record *> &SingletonRegisters, + AsmVariantInfo const &Variant, bool HasMnemonicFirst) { AsmVariantID = Variant.AsmVariantNo; AsmString = CodeGenInstruction::FlattenAsmStringVariants( AsmString, Variant.AsmVariantNo); @@ -972,8 +974,8 @@ void MatchableInfo::initialize(const AsmMatcherInfo &Info, // Collect singleton registers, if used. for (MatchableInfo::AsmOperand &Op : AsmOperands) { extractSingletonRegisterForAsmOperand(Op, Info, Variant.RegisterPrefix); - if (Record *Reg = Op.SingletonReg) - SingletonRegisters.insert(Reg); + if (Op.SingletonReg) + SingletonRegisters.insert(Op.SingletonReg); } const RecordVal *DepMask = TheDef->getValue("DeprecatedFeatureMask"); @@ -1253,7 +1255,7 @@ struct LessRegisterSet { }; void AsmMatcherInfo::buildRegisterClasses( - SmallPtrSetImpl<Record *> &SingletonRegisters) { + SmallPtrSetImpl<const Record *> &SingletonRegisters) { const auto &Registers = Target.getRegBank().getRegisters(); auto &RegClassList = Target.getRegBank().getRegClasses(); @@ -1268,14 +1270,14 @@ void AsmMatcherInfo::buildRegisterClasses( RegisterSet(RC.getOrder().begin(), RC.getOrder().end())); // Add any required singleton sets. - for (Record *Rec : SingletonRegisters) { + for (const Record *Rec : SingletonRegisters) { RegisterSets.insert(RegisterSet(&Rec, &Rec + 1)); } // Introduce derived sets where necessary (when a register does not determine // a unique register set class), and build the mapping of registers to the set // they should classify to. - std::map<Record *, RegisterSet> RegisterMap; + std::map<const Record *, RegisterSet> RegisterMap; for (const CodeGenRegister &CGR : Registers) { // Compute the intersection of all sets containing this register. RegisterSet ContainingSet; @@ -1369,7 +1371,7 @@ void AsmMatcherInfo::buildRegisterClasses( RegisterClasses[It.first] = RegisterSetClasses[It.second]; // Name the register classes which correspond to singleton registers. - for (Record *Rec : SingletonRegisters) { + for (const Record *Rec : SingletonRegisters) { ClassInfo *CI = RegisterClasses[Rec]; assert(CI && "Missing singleton register class info!"); @@ -1526,7 +1528,7 @@ void AsmMatcherInfo::buildInfo() { // Parse the instructions; we need to do this first so that we can gather the // singleton register classes. - SmallPtrSet<Record *, 16> SingletonRegisters; + SmallPtrSet<const Record *, 16> SingletonRegisters; unsigned VariantCount = Target.getAsmParserVariantCount(); for (unsigned VC = 0; VC != VariantCount; ++VC) { Record *AsmVariant = Target.getAsmParserVariant(VC); @@ -1617,7 +1619,7 @@ void AsmMatcherInfo::buildInfo() { StringRef Token = Op.Token; // Check for singleton registers. - if (Record *RegRecord = Op.SingletonReg) { + if (const Record *RegRecord = Op.SingletonReg) { Op.Class = RegisterClasses[RegRecord]; assert(Op.Class && Op.Class->Registers.size() == 1 && "Unexpected class for singleton register"); diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp index ee58cad358a4f1..3f361c3b861b66 100644 --- a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp +++ b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp @@ -158,7 +158,7 @@ void CodeGenSubRegIndex::computeConcatTransitiveClosure() { // CodeGenRegister //===----------------------------------------------------------------------===// -CodeGenRegister::CodeGenRegister(Record *R, unsigned Enum) +CodeGenRegister::CodeGenRegister(const Record *R, unsigned Enum) : TheDef(R), EnumValue(Enum), CostPerUse(R->getValueAsListOfInts("CostPerUse")), CoveredBySubRegs(R->getValueAsBit("CoveredBySubRegs")), @@ -657,10 +657,10 @@ struct TupleExpander : SetTheory::Expander { RecordKeeper &RK = Def->getRecords(); for (unsigned n = 0; n != Length; ++n) { std::string Name; - Record *Proto = Lists[0][n]; + const Record *Proto = Lists[0][n]; std::vector<Init *> Tuple; for (unsigned i = 0; i != Dim; ++i) { - Record *Reg = Lists[i][n]; + const Record *Reg = Lists[i][n]; if (i) Name += '_'; Name += Reg->getName(); @@ -1198,18 +1198,17 @@ CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records, Idx.updateComponents(*this); // Read in the register and register tuple definitions. - std::vector<Record *> Regs = Records.getAllDerivedDefinitions("Register"); + const RecordKeeper &RC = Records; + std::vector<const Record *> Regs = RC.getAllDerivedDefinitions("Register"); if (!Regs.empty() && Regs[0]->isSubClassOf("X86Reg")) { // For X86, we need to sort Registers and RegisterTuples together to list // new registers and register tuples at a later position. So that we can // reduce unnecessary iterations on unsupported registers in LiveVariables. // TODO: Remove this logic when migrate from LiveVariables to LiveIntervals // completely. - std::vector<Record *> Tups = - Records.getAllDerivedDefinitions("RegisterTuples"); - for (Record *R : Tups) { + for (const Record *R : Records.getAllDerivedDefinitions("RegisterTuples")) { // Expand tuples and merge the vectors - std::vector<Record *> TupRegs = *Sets.expand(R); + std::vector<const Record *> TupRegs = *Sets.expand(R); Regs.insert(Regs.end(), TupRegs.begin(), TupRegs.end()); } @@ -1224,13 +1223,10 @@ CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records, getReg(Regs[i]); // Expand tuples and number the new registers. - std::vector<Record *> Tups = - Records.getAllDerivedDefinitions("RegisterTuples"); - - for (Record *R : Tups) { - std::vector<Record *> TupRegs = *Sets.expand(R); + for (Record *R : Records.getAllDerivedDefinitions("RegisterTuples")) { + std::vector<const Record *> TupRegs = *Sets.expand(R); llvm::sort(TupRegs, LessRecordRegister()); - for (Record *RC : TupRegs) + for (const Record *RC : TupRegs) getReg(RC); } } @@ -1342,7 +1338,7 @@ CodeGenRegBank::findSubRegIdx(const Record *Def) const { return Def2SubRegIdx.lookup(Def); } -CodeGenRegister *CodeGenRegBank::getReg(Record *Def) { +CodeGenRegister *CodeGenRegBank::getReg(const Record *Def) { CodeGenRegister *&Reg = Def2Reg[Def]; if (Reg) return Reg; @@ -2508,7 +2504,8 @@ CodeGenRegBank::getMinimalPhysRegClass(Record *RegRecord, return BestRC; } -BitVector CodeGenRegBank::computeCoveredRegisters(ArrayRef<Record *> Regs) { +BitVector +CodeGenRegBank::computeCoveredRegisters(ArrayRef<const Record *> Regs) { SetVector<const CodeGenRegister *> Set; // First add Regs with all sub-registers. diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.h b/llvm/utils/TableGen/Common/CodeGenRegisters.h index c0be8cdbf36c8a..afd0b8312f4260 100644 --- a/llvm/utils/TableGen/Common/CodeGenRegisters.h +++ b/llvm/utils/TableGen/Common/CodeGenRegisters.h @@ -172,7 +172,7 @@ class CodeGenSubRegIndex { /// CodeGenRegister - Represents a register definition. class CodeGenRegister { public: - Record *TheDef; + const Record *TheDef; unsigned EnumValue; std::vector<int64_t> CostPerUse; bool CoveredBySubRegs = true; @@ -184,7 +184,7 @@ class CodeGenRegister { typedef std::map<CodeGenSubRegIndex *, CodeGenRegister *, deref<std::less<>>> SubRegMap; - CodeGenRegister(Record *R, unsigned Enum); + CodeGenRegister(const Record *R, unsigned Enum); StringRef getName() const; @@ -314,7 +314,7 @@ inline bool operator==(const CodeGenRegister &A, const CodeGenRegister &B) { class CodeGenRegisterClass { CodeGenRegister::Vec Members; // Allocation orders. Order[0] always contains all registers in Members. - std::vector<SmallVector<Record *, 16>> Orders; + std::vector<SmallVector<const Record *, 16>> Orders; // Bit mask of sub-classes including this, indexed by their EnumValue. BitVector SubClasses; // List of super-classes, topologocally ordered to have the larger classes @@ -452,7 +452,9 @@ class CodeGenRegisterClass { // Returns an ordered list of class members. // The order of registers is the same as in the .td file. // No = 0 is the default allocation order, No = 1 is the first alternative. - ArrayRef<Record *> getOrder(unsigned No = 0) const { return Orders[No]; } + ArrayRef<const Record *> getOrder(unsigned No = 0) const { + return Orders[No]; + } // Return the total number of allocation orders available. unsigned getNumOrders() const { return Orders.size(); } @@ -594,7 +596,7 @@ class CodeGenRegBank { // Registers. std::deque<CodeGenRegister> Registers; StringMap<CodeGenRegister *> RegistersByName; - DenseMap<Record *, CodeGenRegister *> Def2Reg; + DenseMap<const Record *, CodeGenRegister *> Def2Reg; unsigned NumNativeRegUnits; std::map<TopoSigId, unsigned> TopoSigs; @@ -713,7 +715,7 @@ class CodeGenRegBank { } // Find a register from its Record def. - CodeGenRegister *getReg(Record *); + CodeGenRegister *getReg(const Record *); // Get a Register's index into the Registers array. unsigned getRegIndex(const CodeGenRegister *Reg) const { @@ -846,7 +848,7 @@ class CodeGenRegBank { // // This is used to compute the mask of call-preserved registers from a list // of callee-saves. - BitVector computeCoveredRegisters(ArrayRef<Record *> Regs); + BitVector computeCoveredRegisters(ArrayRef<const Record *> Regs); // Bit mask of lanes that cover their registers. A sub-register index whose // LaneMask is contained in CoveringLanes will be completely covered by diff --git a/llvm/utils/TableGen/Common/CodeGenSchedule.cpp b/llvm/utils/TableGen/Common/CodeGenSchedule.cpp index 5c266808f2e272..0a48feab867cf6 100644 --- a/llvm/utils/TableGen/Common/CodeGenSchedule.cpp +++ b/llvm/utils/TableGen/Common/CodeGenSchedule.cpp @@ -986,8 +986,8 @@ CodeGenSchedModels::createSchedClassName(Record *ItinClassDef, return Name; } -std::string CodeGenSchedModels::createSchedClassName(const RecVec &InstDefs) { - +std::string +CodeGenSchedModels::createSchedClassName(const ConstRecVec &InstDefs) { std::string Name; ListSeparator LS("_"); for (const Record *InstDef : InstDefs) { @@ -1039,13 +1039,13 @@ void CodeGenSchedModels::createInstRWClass(Record *InstRWDef) { // intersects with an existing class via a previous InstRWDef. Instrs that do // not intersect with an existing class refer back to their former class as // determined from ItinDef or SchedRW. - SmallMapVector<unsigned, SmallVector<Record *, 8>, 4> ClassInstrs; + SmallMapVector<unsigned, SmallVector<const Record *, 8>, 4> ClassInstrs; // Sort Instrs into sets. - const RecVec *InstDefs = Sets.expand(InstRWDef); + const ConstRecVec *InstDefs = Sets.expand(InstRWDef); if (InstDefs->empty()) PrintFatalError(InstRWDef->getLoc(), "No matching instruction opcodes"); - for (Record *InstDef : *InstDefs) { + for (const Record *InstDef : *InstDefs) { InstClassMapTy::const_iterator Pos = InstrClassMap.find(InstDef); if (Pos == InstrClassMap.end()) PrintFatalError(InstDef->getLoc(), "No sched class for instruction."); @@ -1056,16 +1056,17 @@ void CodeGenSchedModels::createInstRWClass(Record *InstRWDef) { // the Instrs to it. for (auto &Entry : ClassInstrs) { unsigned OldSCIdx = Entry.first; - ArrayRef<Record *> InstDefs = Entry.second; + ArrayRef<const Record *> InstDefs = Entry.second; // If the all instrs in the current class are accounted for, then leave // them mapped to their old class. if (OldSCIdx) { const RecVec &RWDefs = SchedClasses[OldSCIdx].InstRWs; if (!RWDefs.empty()) { - const RecVec *OrigInstDefs = Sets.expand(RWDefs[0]); - unsigned OrigNumInstrs = count_if(*OrigInstDefs, [&](Record *OIDef) { - return InstrClassMap[OIDef] == OldSCIdx; - }); + const ConstRecVec *OrigInstDefs = Sets.expand(RWDefs[0]); + unsigned OrigNumInstrs = + count_if(*OrigInstDefs, [&](const Record *OIDef) { + return InstrClassMap[OIDef] == OldSCIdx; + }); if (OrigNumInstrs == InstDefs.size()) { assert(SchedClasses[OldSCIdx].ProcIndices[0] == 0 && "expected a generic SchedClass"); @@ -1125,7 +1126,7 @@ void CodeGenSchedModels::createInstRWClass(Record *InstRWDef) { } } // Map each Instr to this new class. - for (Record *InstDef : InstDefs) + for (const Record *InstDef : InstDefs) InstrClassMap[InstDef] = SCIdx; SC.InstRWs.push_back(InstRWDef); } @@ -1262,8 +1263,8 @@ void CodeGenSchedModels::inferFromInstRWs(unsigned SCIdx) { for (unsigned I = 0, E = SchedClasses[SCIdx].InstRWs.size(); I != E; ++I) { assert(SchedClasses[SCIdx].InstRWs.size() == E && "InstrRWs was mutated!"); Record *Rec = SchedClasses[SCIdx].InstRWs[I]; - const RecVec *InstDefs = Sets.expand(Rec); - RecIter II = InstDefs->begin(), IE = InstDefs->end(); + const std::vector<const Record *> *InstDefs = Sets.expand(Rec); + ConstRecIter II = InstDefs->begin(), IE = InstDefs->end(); for (; II != IE; ++II) { if (InstrClassMap[*II] == SCIdx) break; diff --git a/llvm/utils/TableGen/Common/CodeGenSchedule.h b/llvm/utils/TableGen/Common/CodeGenSchedule.h index 22c9b076aeb9f6..57a0986a6b0ca0 100644 --- a/llvm/utils/TableGen/Common/CodeGenSchedule.h +++ b/llvm/utils/TableGen/Common/CodeGenSchedule.h @@ -34,10 +34,12 @@ class CodeGenSchedModels; class CodeGenInstruction; using RecVec = std::vector<Record *>; -using RecIter = std::vector<Record *>::const_iterator; +using RecIter = RecVec::const_iterator; +using ConstRecVec = std::vector<const Record *>; +using ConstRecIter = ConstRecVec::const_iterator; using IdxVec = std::vector<unsigned>; -using IdxIter = std::vector<unsigned>::const_iterat... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/107692 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
