https://github.com/jurahul updated
https://github.com/llvm/llvm-project/pull/107692
>From b11f8fbde5cc005e4667877ed60954f36abcec0c Mon Sep 17 00:00:00 2001
From: Rahul Joshi <rjo...@nvidia.com>
Date: Sat, 7 Sep 2024 04:33:09 -0700
Subject: [PATCH] [TableGen] Change SetTheory set/vec to use consr Record *
Change SetTheory::RecSet/RecVec to use const Record pointers.
---
clang/utils/TableGen/NeonEmitter.cpp | 2 +-
llvm/include/llvm/TableGen/Record.h | 4 +-
llvm/include/llvm/TableGen/SetTheory.h | 4 +-
llvm/lib/TableGen/Record.cpp | 6 +--
llvm/utils/TableGen/AsmMatcherEmitter.cpp | 38 ++++++++++---------
.../TableGen/Common/CodeGenRegisters.cpp | 29 +++++++-------
llvm/utils/TableGen/Common/CodeGenRegisters.h | 16 ++++----
.../utils/TableGen/Common/CodeGenSchedule.cpp | 27 ++++++-------
llvm/utils/TableGen/Common/CodeGenSchedule.h | 10 +++--
llvm/utils/TableGen/RegisterInfoEmitter.cpp | 30 +++++++--------
llvm/utils/TableGen/TableGen.cpp | 2 +-
11 files changed, 86 insertions(+), 82 deletions(-)
diff --git a/clang/utils/TableGen/NeonEmitter.cpp
b/clang/utils/TableGen/NeonEmitter.cpp
index e0d7b0db7f5780..4707ce1ea3b792 100644
--- a/clang/utils/TableGen/NeonEmitter.cpp
+++ b/clang/utils/TableGen/NeonEmitter.cpp
@@ -1636,7 +1636,7 @@ std::pair<Type, std::string>
Intrinsic::DagEmitter::emitDagShuffle(DagInit *DI){
int64_t VectorSize = cast<IntInit>(Expr->getArg(0))->getValue();
VectorSize /= ElementSize;
- std::vector<Record *> Revved;
+ std::vector<const Record *> Revved;
for (unsigned VI = 0; VI < Elts2.size(); VI += VectorSize) {
for (int LI = VectorSize - 1; LI >= 0; --LI) {
Revved.push_back(Elts2[VI + LI]);
diff --git a/llvm/include/llvm/TableGen/Record.h
b/llvm/include/llvm/TableGen/Record.h
index 98c8fd0ca051f9..dc86f28a453285 100644
--- a/llvm/include/llvm/TableGen/Record.h
+++ b/llvm/include/llvm/TableGen/Record.h
@@ -1669,7 +1669,7 @@ class Record {
RecordKeeper &TrackedRecords;
// The DefInit corresponding to this record.
- DefInit *CorrespondingDefInit = nullptr;
+ mutable DefInit *CorrespondingDefInit = nullptr;
// Unique record ID.
unsigned ID;
@@ -1736,7 +1736,7 @@ class Record {
RecordRecTy *getType() const;
/// get the corresponding DefInit.
- DefInit *getDefInit();
+ DefInit *getDefInit() const;
bool isClass() const { return Kind == RK_Class; }
diff --git a/llvm/include/llvm/TableGen/SetTheory.h
b/llvm/include/llvm/TableGen/SetTheory.h
index 954453b783d4d8..771dcff2f214c3 100644
--- a/llvm/include/llvm/TableGen/SetTheory.h
+++ b/llvm/include/llvm/TableGen/SetTheory.h
@@ -64,8 +64,8 @@ class Record;
class SetTheory {
public:
- using RecVec = std::vector<Record *>;
- using RecSet = SmallSetVector<Record *, 16>;
+ using RecVec = std::vector<const Record *>;
+ using RecSet = SmallSetVector<const Record *, 16>;
/// Operator - A callback representing a DAG operator.
class Operator {
diff --git a/llvm/lib/TableGen/Record.cpp b/llvm/lib/TableGen/Record.cpp
index 85516b7b9f20aa..26f45d5bb8a3b7 100644
--- a/llvm/lib/TableGen/Record.cpp
+++ b/llvm/lib/TableGen/Record.cpp
@@ -2802,10 +2802,10 @@ RecordRecTy *Record::getType() const {
return RecordRecTy::get(TrackedRecords, DirectSCs);
}
-DefInit *Record::getDefInit() {
+DefInit *Record::getDefInit() const {
if (!CorrespondingDefInit) {
- CorrespondingDefInit =
- new (TrackedRecords.getImpl().Allocator) DefInit(this);
+ CorrespondingDefInit = new (TrackedRecords.getImpl().Allocator)
+ DefInit(const_cast<Record *>(this));
}
return CorrespondingDefInit;
}
diff --git a/llvm/utils/TableGen/AsmMatcherEmitter.cpp
b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
index f351087ad212f7..574a3344a02f8d 100644
--- a/llvm/utils/TableGen/AsmMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
@@ -140,7 +140,7 @@ class AsmMatcherInfo;
// RegisterSets can be seen in the outputted AsmMatcher tables occasionally,
and
// can even affect compiler output (at least seen in diagnostics produced when
// all matches fail). So we use a type that sorts them consistently.
-typedef std::set<Record *, LessRecordByID> RegisterSet;
+typedef std::set<const Record *, LessRecordByID> RegisterSet;
class AsmMatcherEmitter {
RecordKeeper &Records;
@@ -242,7 +242,7 @@ struct ClassInfo {
if (!isRegisterClass() || !RHS.isRegisterClass())
return false;
- std::vector<Record *> Tmp;
+ std::vector<const Record *> Tmp;
std::set_intersection(Registers.begin(), Registers.end(),
RHS.Registers.begin(), RHS.Registers.end(),
std::back_inserter(Tmp), LessRecordByID());
@@ -403,7 +403,7 @@ struct MatchableInfo {
bool IsIsolatedToken;
/// Register record if this token is singleton register.
- Record *SingletonReg;
+ const Record *SingletonReg;
explicit AsmOperand(bool IsIsolatedToken, StringRef T)
: Token(T), Class(nullptr), SubOpIdx(-1),
@@ -582,7 +582,7 @@ struct MatchableInfo {
void formTwoOperandAlias(StringRef Constraint);
void initialize(const AsmMatcherInfo &Info,
- SmallPtrSetImpl<Record *> &SingletonRegisters,
+ SmallPtrSetImpl<const Record *> &SingletonRegisters,
AsmVariantInfo const &Variant, bool HasMnemonicFirst);
/// validate - Return true if this matchable is a valid thing to match
against
@@ -757,7 +757,8 @@ class AsmMatcherInfo {
std::vector<OperandMatchEntry> OperandMatchInfo;
/// Map of Register records to their class information.
- typedef std::map<Record *, ClassInfo *, LessRecordByID> RegisterClassesTy;
+ typedef std::map<const Record *, ClassInfo *, LessRecordByID>
+ RegisterClassesTy;
RegisterClassesTy RegisterClasses;
/// Map of Predicate records to their subtarget information.
@@ -784,7 +785,8 @@ class AsmMatcherInfo {
/// buildRegisterClasses - Build the ClassInfo* instances for register
/// classes.
- void buildRegisterClasses(SmallPtrSetImpl<Record *> &SingletonRegisters);
+ void
+ buildRegisterClasses(SmallPtrSetImpl<const Record *> &SingletonRegisters);
/// buildOperandClasses - Build the ClassInfo* instances for user defined
/// operand classes.
@@ -935,10 +937,10 @@ static void
extractSingletonRegisterForAsmOperand(MatchableInfo::AsmOperand &Op,
// be some random non-register token, just ignore it.
}
-void MatchableInfo::initialize(const AsmMatcherInfo &Info,
- SmallPtrSetImpl<Record *> &SingletonRegisters,
- AsmVariantInfo const &Variant,
- bool HasMnemonicFirst) {
+void MatchableInfo::initialize(
+ const AsmMatcherInfo &Info,
+ SmallPtrSetImpl<const Record *> &SingletonRegisters,
+ AsmVariantInfo const &Variant, bool HasMnemonicFirst) {
AsmVariantID = Variant.AsmVariantNo;
AsmString = CodeGenInstruction::FlattenAsmStringVariants(
AsmString, Variant.AsmVariantNo);
@@ -972,8 +974,8 @@ void MatchableInfo::initialize(const AsmMatcherInfo &Info,
// Collect singleton registers, if used.
for (MatchableInfo::AsmOperand &Op : AsmOperands) {
extractSingletonRegisterForAsmOperand(Op, Info, Variant.RegisterPrefix);
- if (Record *Reg = Op.SingletonReg)
- SingletonRegisters.insert(Reg);
+ if (Op.SingletonReg)
+ SingletonRegisters.insert(Op.SingletonReg);
}
const RecordVal *DepMask = TheDef->getValue("DeprecatedFeatureMask");
@@ -1253,7 +1255,7 @@ struct LessRegisterSet {
};
void AsmMatcherInfo::buildRegisterClasses(
- SmallPtrSetImpl<Record *> &SingletonRegisters) {
+ SmallPtrSetImpl<const Record *> &SingletonRegisters) {
const auto &Registers = Target.getRegBank().getRegisters();
auto &RegClassList = Target.getRegBank().getRegClasses();
@@ -1268,14 +1270,14 @@ void AsmMatcherInfo::buildRegisterClasses(
RegisterSet(RC.getOrder().begin(), RC.getOrder().end()));
// Add any required singleton sets.
- for (Record *Rec : SingletonRegisters) {
+ for (const Record *Rec : SingletonRegisters) {
RegisterSets.insert(RegisterSet(&Rec, &Rec + 1));
}
// Introduce derived sets where necessary (when a register does not determine
// a unique register set class), and build the mapping of registers to the
set
// they should classify to.
- std::map<Record *, RegisterSet> RegisterMap;
+ std::map<const Record *, RegisterSet> RegisterMap;
for (const CodeGenRegister &CGR : Registers) {
// Compute the intersection of all sets containing this register.
RegisterSet ContainingSet;
@@ -1369,7 +1371,7 @@ void AsmMatcherInfo::buildRegisterClasses(
RegisterClasses[It.first] = RegisterSetClasses[It.second];
// Name the register classes which correspond to singleton registers.
- for (Record *Rec : SingletonRegisters) {
+ for (const Record *Rec : SingletonRegisters) {
ClassInfo *CI = RegisterClasses[Rec];
assert(CI && "Missing singleton register class info!");
@@ -1526,7 +1528,7 @@ void AsmMatcherInfo::buildInfo() {
// Parse the instructions; we need to do this first so that we can gather the
// singleton register classes.
- SmallPtrSet<Record *, 16> SingletonRegisters;
+ SmallPtrSet<const Record *, 16> SingletonRegisters;
unsigned VariantCount = Target.getAsmParserVariantCount();
for (unsigned VC = 0; VC != VariantCount; ++VC) {
Record *AsmVariant = Target.getAsmParserVariant(VC);
@@ -1617,7 +1619,7 @@ void AsmMatcherInfo::buildInfo() {
StringRef Token = Op.Token;
// Check for singleton registers.
- if (Record *RegRecord = Op.SingletonReg) {
+ if (const Record *RegRecord = Op.SingletonReg) {
Op.Class = RegisterClasses[RegRecord];
assert(Op.Class && Op.Class->Registers.size() == 1 &&
"Unexpected class for singleton register");
diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
index 1d6f8c6b4fd883..85065a3ca23228 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
@@ -158,7 +158,7 @@ void CodeGenSubRegIndex::computeConcatTransitiveClosure() {
// CodeGenRegister
//===----------------------------------------------------------------------===//
-CodeGenRegister::CodeGenRegister(Record *R, unsigned Enum)
+CodeGenRegister::CodeGenRegister(const Record *R, unsigned Enum)
: TheDef(R), EnumValue(Enum),
CostPerUse(R->getValueAsListOfInts("CostPerUse")),
CoveredBySubRegs(R->getValueAsBit("CoveredBySubRegs")),
@@ -657,10 +657,10 @@ struct TupleExpander : SetTheory::Expander {
RecordKeeper &RK = Def->getRecords();
for (unsigned n = 0; n != Length; ++n) {
std::string Name;
- Record *Proto = Lists[0][n];
+ const Record *Proto = Lists[0][n];
std::vector<Init *> Tuple;
for (unsigned i = 0; i != Dim; ++i) {
- Record *Reg = Lists[i][n];
+ const Record *Reg = Lists[i][n];
if (i)
Name += '_';
Name += Reg->getName();
@@ -1198,18 +1198,17 @@ CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records,
Idx.updateComponents(*this);
// Read in the register and register tuple definitions.
- std::vector<Record *> Regs = Records.getAllDerivedDefinitions("Register");
+ const RecordKeeper &RC = Records;
+ std::vector<const Record *> Regs = RC.getAllDerivedDefinitions("Register");
if (!Regs.empty() && Regs[0]->isSubClassOf("X86Reg")) {
// For X86, we need to sort Registers and RegisterTuples together to list
// new registers and register tuples at a later position. So that we can
// reduce unnecessary iterations on unsupported registers in LiveVariables.
// TODO: Remove this logic when migrate from LiveVariables to LiveIntervals
// completely.
- std::vector<Record *> Tups =
- Records.getAllDerivedDefinitions("RegisterTuples");
- for (Record *R : Tups) {
+ for (const Record *R : Records.getAllDerivedDefinitions("RegisterTuples"))
{
// Expand tuples and merge the vectors
- std::vector<Record *> TupRegs = *Sets.expand(R);
+ std::vector<const Record *> TupRegs = *Sets.expand(R);
Regs.insert(Regs.end(), TupRegs.begin(), TupRegs.end());
}
@@ -1224,13 +1223,10 @@ CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records,
getReg(Regs[i]);
// Expand tuples and number the new registers.
- std::vector<Record *> Tups =
- Records.getAllDerivedDefinitions("RegisterTuples");
-
- for (Record *R : Tups) {
- std::vector<Record *> TupRegs = *Sets.expand(R);
+ for (Record *R : Records.getAllDerivedDefinitions("RegisterTuples")) {
+ std::vector<const Record *> TupRegs = *Sets.expand(R);
llvm::sort(TupRegs, LessRecordRegister());
- for (Record *RC : TupRegs)
+ for (const Record *RC : TupRegs)
getReg(RC);
}
}
@@ -1342,7 +1338,7 @@ CodeGenRegBank::findSubRegIdx(const Record *Def) const {
return Def2SubRegIdx.lookup(Def);
}
-CodeGenRegister *CodeGenRegBank::getReg(Record *Def) {
+CodeGenRegister *CodeGenRegBank::getReg(const Record *Def) {
CodeGenRegister *&Reg = Def2Reg[Def];
if (Reg)
return Reg;
@@ -2508,7 +2504,8 @@ CodeGenRegBank::getMinimalPhysRegClass(Record *RegRecord,
return BestRC;
}
-BitVector CodeGenRegBank::computeCoveredRegisters(ArrayRef<Record *> Regs) {
+BitVector
+CodeGenRegBank::computeCoveredRegisters(ArrayRef<const Record *> Regs) {
SetVector<const CodeGenRegister *> Set;
// First add Regs with all sub-registers.
diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.h
b/llvm/utils/TableGen/Common/CodeGenRegisters.h
index c0be8cdbf36c8a..afd0b8312f4260 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.h
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.h
@@ -172,7 +172,7 @@ class CodeGenSubRegIndex {
/// CodeGenRegister - Represents a register definition.
class CodeGenRegister {
public:
- Record *TheDef;
+ const Record *TheDef;
unsigned EnumValue;
std::vector<int64_t> CostPerUse;
bool CoveredBySubRegs = true;
@@ -184,7 +184,7 @@ class CodeGenRegister {
typedef std::map<CodeGenSubRegIndex *, CodeGenRegister *, deref<std::less<>>>
SubRegMap;
- CodeGenRegister(Record *R, unsigned Enum);
+ CodeGenRegister(const Record *R, unsigned Enum);
StringRef getName() const;
@@ -314,7 +314,7 @@ inline bool operator==(const CodeGenRegister &A, const
CodeGenRegister &B) {
class CodeGenRegisterClass {
CodeGenRegister::Vec Members;
// Allocation orders. Order[0] always contains all registers in Members.
- std::vector<SmallVector<Record *, 16>> Orders;
+ std::vector<SmallVector<const Record *, 16>> Orders;
// Bit mask of sub-classes including this, indexed by their EnumValue.
BitVector SubClasses;
// List of super-classes, topologocally ordered to have the larger classes
@@ -452,7 +452,9 @@ class CodeGenRegisterClass {
// Returns an ordered list of class members.
// The order of registers is the same as in the .td file.
// No = 0 is the default allocation order, No = 1 is the first alternative.
- ArrayRef<Record *> getOrder(unsigned No = 0) const { return Orders[No]; }
+ ArrayRef<const Record *> getOrder(unsigned No = 0) const {
+ return Orders[No];
+ }
// Return the total number of allocation orders available.
unsigned getNumOrders() const { return Orders.size(); }
@@ -594,7 +596,7 @@ class CodeGenRegBank {
// Registers.
std::deque<CodeGenRegister> Registers;
StringMap<CodeGenRegister *> RegistersByName;
- DenseMap<Record *, CodeGenRegister *> Def2Reg;
+ DenseMap<const Record *, CodeGenRegister *> Def2Reg;
unsigned NumNativeRegUnits;
std::map<TopoSigId, unsigned> TopoSigs;
@@ -713,7 +715,7 @@ class CodeGenRegBank {
}
// Find a register from its Record def.
- CodeGenRegister *getReg(Record *);
+ CodeGenRegister *getReg(const Record *);
// Get a Register's index into the Registers array.
unsigned getRegIndex(const CodeGenRegister *Reg) const {
@@ -846,7 +848,7 @@ class CodeGenRegBank {
//
// This is used to compute the mask of call-preserved registers from a list
// of callee-saves.
- BitVector computeCoveredRegisters(ArrayRef<Record *> Regs);
+ BitVector computeCoveredRegisters(ArrayRef<const Record *> Regs);
// Bit mask of lanes that cover their registers. A sub-register index whose
// LaneMask is contained in CoveringLanes will be completely covered by
diff --git a/llvm/utils/TableGen/Common/CodeGenSchedule.cpp
b/llvm/utils/TableGen/Common/CodeGenSchedule.cpp
index 5c266808f2e272..0a48feab867cf6 100644
--- a/llvm/utils/TableGen/Common/CodeGenSchedule.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenSchedule.cpp
@@ -986,8 +986,8 @@ CodeGenSchedModels::createSchedClassName(Record
*ItinClassDef,
return Name;
}
-std::string CodeGenSchedModels::createSchedClassName(const RecVec &InstDefs) {
-
+std::string
+CodeGenSchedModels::createSchedClassName(const ConstRecVec &InstDefs) {
std::string Name;
ListSeparator LS("_");
for (const Record *InstDef : InstDefs) {
@@ -1039,13 +1039,13 @@ void CodeGenSchedModels::createInstRWClass(Record
*InstRWDef) {
// intersects with an existing class via a previous InstRWDef. Instrs that do
// not intersect with an existing class refer back to their former class as
// determined from ItinDef or SchedRW.
- SmallMapVector<unsigned, SmallVector<Record *, 8>, 4> ClassInstrs;
+ SmallMapVector<unsigned, SmallVector<const Record *, 8>, 4> ClassInstrs;
// Sort Instrs into sets.
- const RecVec *InstDefs = Sets.expand(InstRWDef);
+ const ConstRecVec *InstDefs = Sets.expand(InstRWDef);
if (InstDefs->empty())
PrintFatalError(InstRWDef->getLoc(), "No matching instruction opcodes");
- for (Record *InstDef : *InstDefs) {
+ for (const Record *InstDef : *InstDefs) {
InstClassMapTy::const_iterator Pos = InstrClassMap.find(InstDef);
if (Pos == InstrClassMap.end())
PrintFatalError(InstDef->getLoc(), "No sched class for instruction.");
@@ -1056,16 +1056,17 @@ void CodeGenSchedModels::createInstRWClass(Record
*InstRWDef) {
// the Instrs to it.
for (auto &Entry : ClassInstrs) {
unsigned OldSCIdx = Entry.first;
- ArrayRef<Record *> InstDefs = Entry.second;
+ ArrayRef<const Record *> InstDefs = Entry.second;
// If the all instrs in the current class are accounted for, then leave
// them mapped to their old class.
if (OldSCIdx) {
const RecVec &RWDefs = SchedClasses[OldSCIdx].InstRWs;
if (!RWDefs.empty()) {
- const RecVec *OrigInstDefs = Sets.expand(RWDefs[0]);
- unsigned OrigNumInstrs = count_if(*OrigInstDefs, [&](Record *OIDef) {
- return InstrClassMap[OIDef] == OldSCIdx;
- });
+ const ConstRecVec *OrigInstDefs = Sets.expand(RWDefs[0]);
+ unsigned OrigNumInstrs =
+ count_if(*OrigInstDefs, [&](const Record *OIDef) {
+ return InstrClassMap[OIDef] == OldSCIdx;
+ });
if (OrigNumInstrs == InstDefs.size()) {
assert(SchedClasses[OldSCIdx].ProcIndices[0] == 0 &&
"expected a generic SchedClass");
@@ -1125,7 +1126,7 @@ void CodeGenSchedModels::createInstRWClass(Record
*InstRWDef) {
}
}
// Map each Instr to this new class.
- for (Record *InstDef : InstDefs)
+ for (const Record *InstDef : InstDefs)
InstrClassMap[InstDef] = SCIdx;
SC.InstRWs.push_back(InstRWDef);
}
@@ -1262,8 +1263,8 @@ void CodeGenSchedModels::inferFromInstRWs(unsigned SCIdx)
{
for (unsigned I = 0, E = SchedClasses[SCIdx].InstRWs.size(); I != E; ++I) {
assert(SchedClasses[SCIdx].InstRWs.size() == E && "InstrRWs was mutated!");
Record *Rec = SchedClasses[SCIdx].InstRWs[I];
- const RecVec *InstDefs = Sets.expand(Rec);
- RecIter II = InstDefs->begin(), IE = InstDefs->end();
+ const std::vector<const Record *> *InstDefs = Sets.expand(Rec);
+ ConstRecIter II = InstDefs->begin(), IE = InstDefs->end();
for (; II != IE; ++II) {
if (InstrClassMap[*II] == SCIdx)
break;
diff --git a/llvm/utils/TableGen/Common/CodeGenSchedule.h
b/llvm/utils/TableGen/Common/CodeGenSchedule.h
index 22c9b076aeb9f6..57a0986a6b0ca0 100644
--- a/llvm/utils/TableGen/Common/CodeGenSchedule.h
+++ b/llvm/utils/TableGen/Common/CodeGenSchedule.h
@@ -34,10 +34,12 @@ class CodeGenSchedModels;
class CodeGenInstruction;
using RecVec = std::vector<Record *>;
-using RecIter = std::vector<Record *>::const_iterator;
+using RecIter = RecVec::const_iterator;
+using ConstRecVec = std::vector<const Record *>;
+using ConstRecIter = ConstRecVec::const_iterator;
using IdxVec = std::vector<unsigned>;
-using IdxIter = std::vector<unsigned>::const_iterator;
+using IdxIter = IdxVec::const_iterator;
/// We have two kinds of SchedReadWrites. Explicitly defined and inferred
/// sequences. TheDef is nonnull for explicit SchedWrites, but Sequence may or
@@ -446,7 +448,7 @@ class CodeGenSchedModels {
// Map each instruction to its unique SchedClass index considering the
// combination of it's itinerary class, SchedRW list, and InstRW records.
- using InstClassMapTy = DenseMap<Record *, unsigned>;
+ using InstClassMapTy = DenseMap<const Record *, unsigned>;
InstClassMapTy InstrClassMap;
std::vector<STIPredicateFunction> STIPredicates;
@@ -602,7 +604,7 @@ class CodeGenSchedModels {
std::string createSchedClassName(Record *ItinClassDef,
ArrayRef<unsigned> OperWrites,
ArrayRef<unsigned> OperReads);
- std::string createSchedClassName(const RecVec &InstDefs);
+ std::string createSchedClassName(const ConstRecVec &InstDefs);
void createInstRWClass(Record *InstRWDef);
void collectProcItins();
diff --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp
b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
index dce6c2ada91744..d1c21ba14f59ae 100644
--- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
@@ -351,7 +351,7 @@ void RegisterInfoEmitter::EmitRegUnitPressure(raw_ostream
&OS,
<< "}\n\n";
}
-using DwarfRegNumsMapPair = std::pair<Record *, std::vector<int64_t>>;
+using DwarfRegNumsMapPair = std::pair<const Record *, std::vector<int64_t>>;
using DwarfRegNumsVecTy = std::vector<DwarfRegNumsMapPair>;
static void finalizeDwarfRegNumsKeys(DwarfRegNumsVecTy &DwarfRegNums) {
@@ -385,7 +385,7 @@ void RegisterInfoEmitter::EmitRegMappingTables(
// First, just pull all provided information to the map
unsigned maxLength = 0;
for (auto &RE : Regs) {
- Record *Reg = RE.TheDef;
+ const Record *Reg = RE.TheDef;
std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
maxLength = std::max((size_t)maxLength, RegNums.size());
DwarfRegNums.emplace_back(Reg, std::move(RegNums));
@@ -416,7 +416,7 @@ void RegisterInfoEmitter::EmitRegMappingTables(
// Store the mapping sorted by the LLVM reg num so lookup can be done
// with a binary search.
- std::map<uint64_t, Record *> Dwarf2LMap;
+ std::map<uint64_t, const Record *> Dwarf2LMap;
for (auto &DwarfRegNum : DwarfRegNums) {
int DwarfRegNo = DwarfRegNum.second[I];
if (DwarfRegNo < 0)
@@ -446,7 +446,7 @@ void RegisterInfoEmitter::EmitRegMappingTables(
}
for (auto &RE : Regs) {
- Record *Reg = RE.TheDef;
+ const Record *Reg = RE.TheDef;
const RecordVal *V = Reg->getValue("DwarfAlias");
if (!V || !V->getValue())
continue;
@@ -510,7 +510,7 @@ void RegisterInfoEmitter::EmitRegMapping(
// to the MCRegisterInfo object.
unsigned maxLength = 0;
for (auto &RE : Regs) {
- Record *Reg = RE.TheDef;
+ const Record *Reg = RE.TheDef;
maxLength = std::max((size_t)maxLength,
Reg->getValueAsListOfInts("DwarfNumbers").size());
}
@@ -1006,7 +1006,7 @@ void RegisterInfoEmitter::runMCDesc(raw_ostream &OS,
CodeGenTarget &Target,
// Emit the register enum value arrays for each RegisterClass
for (const auto &RC : RegisterClasses) {
- ArrayRef<Record *> Order = RC.getOrder();
+ ArrayRef<const Record *> Order = RC.getOrder();
// Give the register class a legal C name if it's anonymous.
const std::string &Name = RC.getName();
@@ -1017,7 +1017,7 @@ void RegisterInfoEmitter::runMCDesc(raw_ostream &OS,
CodeGenTarget &Target,
if (!Order.empty()) {
OS << " // " << Name << " Register Class...\n"
<< " const MCPhysReg " << Name << "[] = {\n ";
- for (Record *Reg : Order) {
+ for (const Record *Reg : Order) {
OS << getQualifiedName(Reg) << ", ";
}
OS << "\n };\n\n";
@@ -1025,7 +1025,7 @@ void RegisterInfoEmitter::runMCDesc(raw_ostream &OS,
CodeGenTarget &Target,
OS << " // " << Name << " Bit set.\n"
<< " const uint8_t " << Name << "Bits[] = {\n ";
BitVectorEmitter BVE;
- for (Record *Reg : Order) {
+ for (const Record *Reg : Order) {
BVE.add(Target.getRegBank().getReg(Reg)->EnumValue);
}
BVE.print(OS);
@@ -1042,7 +1042,7 @@ void RegisterInfoEmitter::runMCDesc(raw_ostream &OS,
CodeGenTarget &Target,
<< "MCRegisterClasses[] = {\n";
for (const auto &RC : RegisterClasses) {
- ArrayRef<Record *> Order = RC.getOrder();
+ ArrayRef<const Record *> Order = RC.getOrder();
std::string RCName = Order.empty() ? "nullptr" : RC.getName();
std::string RCBitsName = Order.empty() ? "nullptr" : RC.getName() + "Bits";
std::string RCBitsSize = Order.empty() ? "0" : "sizeof(" + RCBitsName +
")";
@@ -1068,7 +1068,7 @@ void RegisterInfoEmitter::runMCDesc(raw_ostream &OS,
CodeGenTarget &Target,
// Add entry for NoRegister
OS << " 0,\n";
for (const auto &RE : Regs) {
- Record *Reg = RE.TheDef;
+ const Record *Reg = RE.TheDef;
BitsInit *BI = Reg->getValueAsBitsInit("HWEncoding");
uint64_t Value = 0;
for (unsigned b = 0, be = BI->getNumBits(); b != be; ++b) {
@@ -1206,11 +1206,11 @@ void RegisterInfoEmitter::runTargetDesc(raw_ostream
&OS, CodeGenTarget &Target,
const auto &SubRegIndices = RegBank.getSubRegIndices();
// Collect all registers belonging to any allocatable class.
- std::set<Record *> AllocatableRegs;
+ std::set<const Record *> AllocatableRegs;
// Collect allocatable registers.
for (const auto &RC : RegisterClasses) {
- ArrayRef<Record *> Order = RC.getOrder();
+ ArrayRef<const Record *> Order = RC.getOrder();
if (RC.Allocatable)
AllocatableRegs.insert(Order.begin(), Order.end());
@@ -1375,7 +1375,7 @@ void RegisterInfoEmitter::runTargetDesc(raw_ostream &OS,
CodeGenTarget &Target,
<< "static ArrayRef<MCPhysReg> " << RC.getName()
<< "GetRawAllocationOrder(const MachineFunction &MF) {\n";
for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi) {
- ArrayRef<Record *> Elems = RC.getOrder(oi);
+ ArrayRef<const Record *> Elems = RC.getOrder(oi);
if (!Elems.empty()) {
OS << " static const MCPhysReg AltOrder" << oi << "[] = {";
for (unsigned elem = 0; elem != Elems.size(); ++elem)
@@ -1694,7 +1694,7 @@ void RegisterInfoEmitter::runTargetDesc(raw_ostream &OS,
CodeGenTarget &Target,
SetTheory::RecSet OPSet;
RegBank.getSets().evaluate(OPDag, OPSet, CSRSet->getLoc());
Covered |= RegBank.computeCoveredRegisters(
- ArrayRef<Record *>(OPSet.begin(), OPSet.end()));
+ ArrayRef<const Record *>(OPSet.begin(), OPSet.end()));
}
// Add all constant physical registers to the preserved mask:
@@ -1704,7 +1704,7 @@ void RegisterInfoEmitter::runTargetDesc(raw_ostream &OS,
CodeGenTarget &Target,
ConstantSet.insert(Reg.TheDef);
}
Covered |= RegBank.computeCoveredRegisters(
- ArrayRef<Record *>(ConstantSet.begin(), ConstantSet.end()));
+ ArrayRef<const Record *>(ConstantSet.begin(), ConstantSet.end()));
OS << "static const uint32_t " << CSRSet->getName() << "_RegMask[] = { ";
printBitVectorAsHex(OS, Covered, 32);
diff --git a/llvm/utils/TableGen/TableGen.cpp b/llvm/utils/TableGen/TableGen.cpp
index 882410bac081b4..2cc9f364d20cb4 100644
--- a/llvm/utils/TableGen/TableGen.cpp
+++ b/llvm/utils/TableGen/TableGen.cpp
@@ -54,7 +54,7 @@ static void PrintSets(const RecordKeeper &Records,
raw_ostream &OS) {
Sets.addFieldExpander("Set", "Elements");
for (const Record *Rec : Records.getAllDerivedDefinitions("Set")) {
OS << Rec->getName() << " = [";
- const std::vector<Record *> *Elts = Sets.expand(Rec);
+ const std::vector<const Record *> *Elts = Sets.expand(Rec);
assert(Elts && "Couldn't expand Set instance");
for (const Record *Elt : *Elts)
OS << ' ' << Elt->getName();
_______________________________________________
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
