[clang] [llvm] [RISCV] Add sifive-p470 processor (PR #102022)

[Yingwei Zheng via cfe-commits]

================
@@ -266,11 +272,47 @@ def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", 
SiFiveP400Model,
                                        FeatureStdExtZfhmin,
                                        FeatureUnalignedScalarMem,
                                        FeatureUnalignedVectorMem],
-                                      [TuneNoDefaultUnroll,
-                                       TuneConditionalCompressedMoveFusion,
-                                       TuneLUIADDIFusion,
-                                       TuneAUIPCADDIFusion,
-                                       FeaturePostRAScheduler]>;
+                                      SiFiveP400TuneFeatures>;
+
+def SIFIVE_P470 : RISCVProcessorModel<"sifive-p470", SiFiveP400Model,
----------------
dtcxzyw wrote:

The data sheet says P470 is RVA22 compliant. Can we use 
`!listconcat(RVA22S64Features, ...)` here? See the processor definition for 
`SPACEMIT_X60` below.


https://github.com/llvm/llvm-project/pull/102022
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