https://github.com/JaydeepChauhan14 updated
https://github.com/llvm/llvm-project/pull/96860
>From b4a534ad6f811cf0868b7fd1ee641fae8502e171 Mon Sep 17 00:00:00 2001
From: Chauhan Jaydeep Ashwinbhai <chauhan.jaydeep.ashwinb...@intel.com>
Date: Thu, 27 Jun 2024 15:17:50 +0800
Subject: [PATCH 01/14] [X86][MC] Added support for -msse2avx option in llvm-mc
---
llvm/include/llvm/MC/MCTargetOptions.h | 1 +
.../llvm/MC/MCTargetOptionsCommandFlags.h | 2 +
llvm/lib/MC/MCTargetOptions.cpp | 2 +-
llvm/lib/MC/MCTargetOptionsCommandFlags.cpp | 6 ++
.../lib/Target/X86/AsmParser/X86AsmParser.cpp | 20 +++++
llvm/test/MC/AsmParser/sse2avx.s | 74 +++++++++++++++++++
.../utils/TableGen/X86InstrMappingEmitter.cpp | 28 +++++++
7 files changed, 132 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/MC/AsmParser/sse2avx.s
diff --git a/llvm/include/llvm/MC/MCTargetOptions.h
b/llvm/include/llvm/MC/MCTargetOptions.h
index 0cf2806bd4804..90fe356d47077 100644
--- a/llvm/include/llvm/MC/MCTargetOptions.h
+++ b/llvm/include/llvm/MC/MCTargetOptions.h
@@ -55,6 +55,7 @@ class MCTargetOptions {
bool ShowMCEncoding : 1;
bool ShowMCInst : 1;
bool AsmVerbose : 1;
+ bool SSE2AVX : 1;
/// Preserve Comments in Assembly.
bool PreserveAsmComments : 1;
diff --git a/llvm/include/llvm/MC/MCTargetOptionsCommandFlags.h
b/llvm/include/llvm/MC/MCTargetOptionsCommandFlags.h
index dc33f7461ab28..2b5f74fc6c1d8 100644
--- a/llvm/include/llvm/MC/MCTargetOptionsCommandFlags.h
+++ b/llvm/include/llvm/MC/MCTargetOptionsCommandFlags.h
@@ -41,6 +41,8 @@ bool getEmitCompactUnwindNonCanonical();
bool getShowMCInst();
+bool getSSE2AVX();
+
bool getFatalWarnings();
bool getNoWarn();
diff --git a/llvm/lib/MC/MCTargetOptions.cpp b/llvm/lib/MC/MCTargetOptions.cpp
index bff4b8da2fb1b..227d9fc347e71 100644
--- a/llvm/lib/MC/MCTargetOptions.cpp
+++ b/llvm/lib/MC/MCTargetOptions.cpp
@@ -16,7 +16,7 @@ MCTargetOptions::MCTargetOptions()
MCNoWarn(false), MCNoDeprecatedWarn(false), MCNoTypeCheck(false),
MCSaveTempLabels(false), MCIncrementalLinkerCompatible(false),
FDPIC(false), ShowMCEncoding(false), ShowMCInst(false),
AsmVerbose(false),
- PreserveAsmComments(true), Dwarf64(false),
+ SSE2AVX(false), PreserveAsmComments(true), Dwarf64(false),
EmitDwarfUnwind(EmitDwarfUnwindType::Default),
MCUseDwarfDirectory(DefaultDwarfDirectory),
EmitCompactUnwindNonCanonical(false), PPCUseFullRegisterNames(false) {}
diff --git a/llvm/lib/MC/MCTargetOptionsCommandFlags.cpp
b/llvm/lib/MC/MCTargetOptionsCommandFlags.cpp
index 2c378643797da..6de42fa981e6d 100644
--- a/llvm/lib/MC/MCTargetOptionsCommandFlags.cpp
+++ b/llvm/lib/MC/MCTargetOptionsCommandFlags.cpp
@@ -42,6 +42,7 @@ MCOPT(bool, Dwarf64)
MCOPT(EmitDwarfUnwindType, EmitDwarfUnwind)
MCOPT(bool, EmitCompactUnwindNonCanonical)
MCOPT(bool, ShowMCInst)
+MCOPT(bool, SSE2AVX)
MCOPT(bool, FatalWarnings)
MCOPT(bool, NoWarn)
MCOPT(bool, NoDeprecatedWarn)
@@ -107,6 +108,10 @@
llvm::mc::RegisterMCTargetOptionsFlags::RegisterMCTargetOptionsFlags() {
cl::desc("Emit internal instruction representation to assembly file"));
MCBINDOPT(ShowMCInst);
+ static cl::opt<bool> SSE2AVX(
+ "msse2avx", cl::desc("Convert SSE Instructions to AVX Instructions"));
+ MCBINDOPT(SSE2AVX);
+
static cl::opt<bool> FatalWarnings("fatal-warnings",
cl::desc("Treat warnings as errors"));
MCBINDOPT(FatalWarnings);
@@ -156,6 +161,7 @@ MCTargetOptions llvm::mc::InitMCTargetOptionsFromFlags() {
Options.Dwarf64 = getDwarf64();
Options.DwarfVersion = getDwarfVersion();
Options.ShowMCInst = getShowMCInst();
+ Options.SSE2AVX = getSSE2AVX();
Options.ABIName = getABIName();
Options.MCFatalWarnings = getFatalWarnings();
Options.MCNoWarn = getNoWarn();
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index dbea42d55b5fc..ab70fdbc70caa 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -58,6 +58,10 @@ static bool checkScale(unsigned Scale, StringRef &ErrMsg) {
namespace {
+// Including the generated SSE2AVX compression tables.
+#define GET_X86_SSE2AVX_TABLE
+#include "X86GenInstrMapping.inc"
+
static const char OpPrecedence[] = {
0, // IC_OR
1, // IC_XOR
@@ -4141,6 +4145,15 @@ unsigned X86AsmParser::checkTargetMatchPredicate(MCInst
&Inst) {
return Match_Success;
}
+void ReplaceSSE2AVXOpcode(llvm::MCInst &Inst) {
+ ArrayRef<X86TableEntry> Table{X86SSE2AVXTable};
+ unsigned Opcode = Inst.getOpcode();
+ const auto I = llvm::lower_bound(Table, Opcode);
+ if (I != Table.end() && I->OldOpc == Opcode) {
+ Inst.setOpcode(I->NewOpc);
+ }
+}
+
bool X86AsmParser::matchAndEmitATTInstruction(
SMLoc IDLoc, unsigned &Opcode, MCInst &Inst, OperandVector &Operands,
MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm) {
@@ -4159,6 +4172,13 @@ bool X86AsmParser::matchAndEmitATTInstruction(
SwitchMode(X86::Is16Bit);
ForcedDataPrefix = 0;
}
+
+ // When "-msse2avx" option is enabled ReplaceSSE2AVXOpcode method will
+ // replace SSE instruction with equivalent AVX instruction using mapping
given
+ // in table GET_X86_SSE2AVX_TABLE
+ if (MCOptions.SSE2AVX)
+ ReplaceSSE2AVXOpcode(Inst);
+
switch (OriginalError) {
default: llvm_unreachable("Unexpected match result!");
case Match_Success:
diff --git a/llvm/test/MC/AsmParser/sse2avx.s b/llvm/test/MC/AsmParser/sse2avx.s
new file mode 100644
index 0000000000000..ee0c1251478b3
--- /dev/null
+++ b/llvm/test/MC/AsmParser/sse2avx.s
@@ -0,0 +1,74 @@
+# RUN: llvm-mc -triple x86_64-unknown-unknown -msse2avx %s | FileCheck %s
+ .text
+# CHECK: vmovsd -352(%rbp), %xmm0
+ movsd -352(%rbp), %xmm0 # xmm0 = mem[0],zero
+# CHECK-NEXT: vunpcklpd %xmm1, %xmm0, %xmm0 # xmm0 = xmm0[0],xmm1[0]
+ unpcklpd %xmm1, %xmm0 # xmm0 = xmm0[0],xmm1[0]
+# CHECK-NEXT: vmovapd %xmm0, -368(%rbp)
+ movapd %xmm0, -368(%rbp)
+# CHECK-NEXT: vmovapd -368(%rbp), %xmm0
+ movapd -368(%rbp), %xmm0
+# CHECK-NEXT: vmovsd -376(%rbp), %xmm1
+ movsd -376(%rbp), %xmm1 # xmm1 = mem[0],zero
+# CHECK-NEXT: vmovsd -384(%rbp), %xmm0
+ movsd -384(%rbp), %xmm0 # xmm0 = mem[0],zero
+# CHECK-NEXT: vunpcklpd %xmm1, %xmm0, %xmm0 # xmm0 = xmm0[0],xmm1[0]
+ unpcklpd %xmm1, %xmm0 # xmm0 = xmm0[0],xmm1[0]
+# CHECK-NEXT: vaddpd %xmm1, %xmm0, %xmm0
+ addpd %xmm1, %xmm0
+# CHECK-NEXT: vmovapd %xmm0, -464(%rbp)
+ movapd %xmm0, -464(%rbp)
+# CHECK-NEXT: vmovaps -304(%rbp), %xmm1
+ movaps -304(%rbp), %xmm1
+# CHECK-NEXT: vpandn %xmm1, %xmm0, %xmm0
+ pandn %xmm1, %xmm0
+# CHECK-NEXT: vmovaps %xmm0, -480(%rbp)
+ movaps %xmm0, -480(%rbp)
+# CHECK-NEXT: vmovss -220(%rbp), %xmm1
+ movss -220(%rbp), %xmm1 # xmm1 = mem[0],zero,zero,zero
+# CHECK-NEXT: vinsertps $16, %xmm1, %xmm0, %xmm0 # xmm0 =
xmm0[0],xmm1[0],xmm0[2,3]
+ insertps $16, %xmm1, %xmm0 # xmm0 =
xmm0[0],xmm1[0],xmm0[2,3]
+# CHECK-NEXT: vmovaps %xmm0, -496(%rbp)
+ movaps %xmm0, -496(%rbp)
+# CHECK-NEXT: vmovss -256(%rbp), %xmm0
+ movss -256(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
+# CHECK-NEXT: vmovaps -192(%rbp), %xmm0
+ movaps -192(%rbp), %xmm0
+# CHECK-NEXT: vdivss %xmm1, %xmm0, %xmm0
+ divss %xmm1, %xmm0
+# CHECK-NEXT: vmovaps %xmm0, -192(%rbp)
+ movaps %xmm0, -192(%rbp)
+# CHECK-NEXT: vmovd -128(%rbp), %xmm0
+ movd -128(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
+# CHECK-NEXT: vpinsrd $1, %edx, %xmm0, %xmm0
+ pinsrd $1, %edx, %xmm0
+# CHECK-NEXT: vmovaps %xmm0, -144(%rbp)
+ movaps %xmm0, -144(%rbp)
+# CHECK-NEXT: vmovd -160(%rbp), %xmm0
+ movd -160(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
+# CHECK-NEXT: vpblendw $170, %xmm1, %xmm0, %xmm0 # xmm0 =
xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7]
+ pblendw $170, %xmm1, %xmm0 # xmm0 =
xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7]
+# CHECK-NEXT: vmovdqa %xmm0, -576(%rbp)
+ movdqa %xmm0, -576(%rbp)
+# CHECK-NEXT: vphsubw %xmm1, %xmm0, %xmm0
+ phsubw %xmm1, %xmm0
+# CHECK-NEXT: vmovdqa %xmm0, -592(%rbp)
+ movdqa %xmm0, -592(%rbp)
+# CHECK-NEXT: vmovaps -496(%rbp), %xmm0
+ movaps -496(%rbp), %xmm0
+# CHECK-NEXT: vroundps $8, %xmm0, %xmm0
+ roundps $8, %xmm0, %xmm0
+# CHECK-NEXT: vmovaps %xmm0, -608(%rbp)
+ movaps %xmm0, -608(%rbp)
+# CHECK-NEXT: vmovapd -432(%rbp), %xmm0
+ movapd -432(%rbp), %xmm0
+# CHECK-NEXT: vpxor %xmm1, %xmm0, %xmm0
+ pxor %xmm1, %xmm0
+# CHECK-NEXT: vmovaps %xmm0, -640(%rbp)
+ movaps %xmm0, -640(%rbp)
+# CHECK-NEXT: vmovapd -32(%rbp), %xmm0
+ movapd -32(%rbp), %xmm0
+# CHECK-NEXT: vmovupd %xmm0, (%rax)
+ movupd %xmm0, (%rax)
+# CHECK-NEXT: vmovsd -656(%rbp), %xmm0
+ movsd -656(%rbp), %xmm0 # xmm0 = mem[0],zero
diff --git a/llvm/utils/TableGen/X86InstrMappingEmitter.cpp
b/llvm/utils/TableGen/X86InstrMappingEmitter.cpp
index 950ff1394b9fd..770943177551f 100644
--- a/llvm/utils/TableGen/X86InstrMappingEmitter.cpp
+++ b/llvm/utils/TableGen/X86InstrMappingEmitter.cpp
@@ -56,6 +56,8 @@ class X86InstrMappingEmitter {
raw_ostream &OS);
void emitND2NonNDTable(ArrayRef<const CodeGenInstruction *> Insts,
raw_ostream &OS);
+ void emitSSE2AVXTable(ArrayRef<const CodeGenInstruction *> Insts,
+ raw_ostream &OS);
// Prints the definition of class X86TableEntry.
void printClassDef(raw_ostream &OS);
@@ -335,6 +337,31 @@ void X86InstrMappingEmitter::emitND2NonNDTable(
printTable(Table, "X86ND2NonNDTable", "GET_X86_ND2NONND_TABLE", OS);
}
+// Method emitSSE2AVXTable will create table GET_X86_SSE2AVX_TABLE for SSE to
+// AVX instruction mapping in X86GenInstrMapping.inc file, In table first entry
+// will be SSE instruction and second entry will be equivalent AVX instruction
+// Example:- "{ X86::ADDPDrm, X86::VADDPDrm },"
+void X86InstrMappingEmitter::emitSSE2AVXTable(
+ ArrayRef<const CodeGenInstruction *> Insts, raw_ostream &OS) {
+ std::vector<Entry> Table;
+ for (const CodeGenInstruction *Inst : Insts) {
+ const Record *Rec = Inst->TheDef;
+ StringRef Name = Rec->getName();
+
+ auto *NewRec = Records.getDef(Name);
+ if (!NewRec)
+ continue;
+
+ std::string NewName = ("V" + Name).str();
+ auto *AVXRec = Records.getDef(NewName);
+ if (!AVXRec)
+ continue;
+ auto &AVXInst = Target.getInstruction(AVXRec);
+ Table.push_back(std::pair(Inst, &AVXInst));
+ }
+ printTable(Table, "X86SSE2AVXTable", "GET_X86_SSE2AVX_TABLE", OS);
+}
+
void X86InstrMappingEmitter::run(raw_ostream &OS) {
emitSourceFileHeader("X86 instruction mapping", OS);
@@ -344,6 +371,7 @@ void X86InstrMappingEmitter::run(raw_ostream &OS) {
emitCompressEVEXTable(Insts, OS);
emitNFTransformTable(Insts, OS);
emitND2NonNDTable(Insts, OS);
+ emitSSE2AVXTable(Insts, OS);
}
} // namespace
>From 95021b655437c68b9874049b66fcadcd3a6b24b8 Mon Sep 17 00:00:00 2001
From: Chauhan Jaydeep Ashwinbhai <chauhan.jaydeep.ashwinb...@intel.com>
Date: Fri, 28 Jun 2024 13:27:14 +0800
Subject: [PATCH 02/14] Addressd review comments
---
llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp | 6 +++---
llvm/test/MC/AsmParser/sse2avx.s | 6 ++++++
llvm/utils/TableGen/X86InstrMappingEmitter.cpp | 7 ++-----
3 files changed, 11 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index ab70fdbc70caa..50cc9ee919fcf 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -4145,7 +4145,7 @@ unsigned X86AsmParser::checkTargetMatchPredicate(MCInst
&Inst) {
return Match_Success;
}
-void ReplaceSSE2AVXOpcode(llvm::MCInst &Inst) {
+void replaceSSE2AVXOpcode(llvm::MCInst &Inst) {
ArrayRef<X86TableEntry> Table{X86SSE2AVXTable};
unsigned Opcode = Inst.getOpcode();
const auto I = llvm::lower_bound(Table, Opcode);
@@ -4173,11 +4173,11 @@ bool X86AsmParser::matchAndEmitATTInstruction(
ForcedDataPrefix = 0;
}
- // When "-msse2avx" option is enabled ReplaceSSE2AVXOpcode method will
+ // When "-msse2avx" option is enabled replaceSSE2AVXOpcode method will
// replace SSE instruction with equivalent AVX instruction using mapping
given
// in table GET_X86_SSE2AVX_TABLE
if (MCOptions.SSE2AVX)
- ReplaceSSE2AVXOpcode(Inst);
+ replaceSSE2AVXOpcode(Inst);
switch (OriginalError) {
default: llvm_unreachable("Unexpected match result!");
diff --git a/llvm/test/MC/AsmParser/sse2avx.s b/llvm/test/MC/AsmParser/sse2avx.s
index ee0c1251478b3..29f2181dfcce8 100644
--- a/llvm/test/MC/AsmParser/sse2avx.s
+++ b/llvm/test/MC/AsmParser/sse2avx.s
@@ -72,3 +72,9 @@
movupd %xmm0, (%rax)
# CHECK-NEXT: vmovsd -656(%rbp), %xmm0
movsd -656(%rbp), %xmm0 # xmm0 = mem[0],zero
+# CHECK-NEXT: extrq $16, $8, %xmm0 # xmm0 =
xmm0[2],zero,zero,zero,zero,zero,zero,zero,xmm0[u,u,u,u,u,u,u,u]
+ extrq $16, $8, %xmm0
+# CHECK-NEXT: insertq $16, $8, %xmm1, %xmm0 # xmm0 =
xmm0[0,1],xmm1[0],xmm0[3,4,5,6,7,u,u,u,u,u,u,u,u]
+ insertq $16, $8, %xmm1, %xmm0
+# CHECK-NEXT: pshufw $1, %mm0, %mm2 # mm2 = mm0[1,0,0,0]
+ pshufw $1, %mm0, %mm2
diff --git a/llvm/utils/TableGen/X86InstrMappingEmitter.cpp
b/llvm/utils/TableGen/X86InstrMappingEmitter.cpp
index 770943177551f..90611de641f30 100644
--- a/llvm/utils/TableGen/X86InstrMappingEmitter.cpp
+++ b/llvm/utils/TableGen/X86InstrMappingEmitter.cpp
@@ -337,17 +337,14 @@ void X86InstrMappingEmitter::emitND2NonNDTable(
printTable(Table, "X86ND2NonNDTable", "GET_X86_ND2NONND_TABLE", OS);
}
-// Method emitSSE2AVXTable will create table GET_X86_SSE2AVX_TABLE for SSE to
-// AVX instruction mapping in X86GenInstrMapping.inc file, In table first entry
-// will be SSE instruction and second entry will be equivalent AVX instruction
-// Example:- "{ X86::ADDPDrm, X86::VADDPDrm },"
void X86InstrMappingEmitter::emitSSE2AVXTable(
ArrayRef<const CodeGenInstruction *> Insts, raw_ostream &OS) {
std::vector<Entry> Table;
for (const CodeGenInstruction *Inst : Insts) {
const Record *Rec = Inst->TheDef;
StringRef Name = Rec->getName();
-
+ if (!isInteresting(Rec))
+ continue;
auto *NewRec = Records.getDef(Name);
if (!NewRec)
continue;
>From 0bf7123acbdae06ebccfc105607b0ccec778c127 Mon Sep 17 00:00:00 2001
From: Chauhan Jaydeep Ashwinbhai <chauhan.jaydeep.ashwinb...@intel.com>
Date: Fri, 28 Jun 2024 20:48:41 +0800
Subject: [PATCH 03/14] Added support for intel syntax
---
.../lib/Target/X86/AsmParser/X86AsmParser.cpp | 6 ++
llvm/test/MC/AsmParser/sse2avx-intel.s | 80 +++++++++++++++++++
2 files changed, 86 insertions(+)
create mode 100644 llvm/test/MC/AsmParser/sse2avx-intel.s
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index 50cc9ee919fcf..644ed451cb18e 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -4513,6 +4513,12 @@ bool X86AsmParser::matchAndEmitIntelInstruction(
/*Len=*/0, UnsizedMemOp->getMemFrontendSize());
}
+ // When "-msse2avx" option is enabled replaceSSE2AVXOpcode method will
+ // replace SSE instruction with equivalent AVX instruction using mapping
given
+ // in table GET_X86_SSE2AVX_TABLE
+ if (MCOptions.SSE2AVX)
+ replaceSSE2AVXOpcode(Inst);
+
// If exactly one matched, then we treat that as a successful match (and the
// instruction will already have been filled in correctly, since the failing
// matches won't have modified it).
diff --git a/llvm/test/MC/AsmParser/sse2avx-intel.s
b/llvm/test/MC/AsmParser/sse2avx-intel.s
new file mode 100644
index 0000000000000..72f3638a41a81
--- /dev/null
+++ b/llvm/test/MC/AsmParser/sse2avx-intel.s
@@ -0,0 +1,80 @@
+# RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel -msse2avx
%s | FileCheck %s
+ .text
+# CHECK: vmovsd -352(%rbp), %xmm0
+ movsd xmm0, qword ptr [rbp - 352] # xmm0 = mem[0],zero
+# CHECK-NEXT: vunpcklpd %xmm1, %xmm0, %xmm0 # xmm0 = xmm0[0],xmm1[0]
+ unpcklpd xmm0, xmm1 # xmm0 = xmm0[0],xmm1[0]
+# CHECK-NEXT: vmovapd %xmm0, -368(%rbp)
+ movapd xmmword ptr [rbp - 368], xmm0
+# CHECK-NEXT: vmovapd -368(%rbp), %xmm0
+ movapd xmm0, xmmword ptr [rbp - 368]
+# CHECK-NEXT: vmovapd %xmm0, -432(%rbp)
+ movapd xmmword ptr [rbp - 432], xmm0
+# CHECK-NEXT: movabsq $4613937818241073152, %rax # imm =
0x4008000000000000
+ movabs rax, 4613937818241073152
+# CHECK-NEXT: vunpcklpd %xmm1, %xmm0, %xmm0 # xmm0 = xmm0[0],xmm1[0]
+ unpcklpd xmm0, xmm1 # xmm0 = xmm0[0],xmm1[0]
+# CHECK-NEXT: vaddpd %xmm1, %xmm0, %xmm0
+ addpd xmm0, xmm1
+# CHECK-NEXT: vmovapd %xmm0, -464(%rbp)
+ movapd xmmword ptr [rbp - 464], xmm0
+# CHECK-NEXT: vmovaps -304(%rbp), %xmm1
+ movaps xmm1, xmmword ptr [rbp - 304]
+# CHECK-NEXT: vpandn %xmm1, %xmm0, %xmm0
+ pandn xmm0, xmm1
+# CHECK-NEXT: vmovaps %xmm0, -480(%rbp)
+ movaps xmmword ptr [rbp - 480], xmm0
+# CHECK-NEXT: vmovss -220(%rbp), %xmm1
+ movss xmm1, dword ptr [rbp - 220] # xmm1 = mem[0],zero,zero,zero
+# CHECK-NEXT: vinsertps $16, %xmm1, %xmm0, %xmm0 # xmm0 =
xmm0[0],xmm1[0],xmm0[2,3]
+ insertps xmm0, xmm1, 16 # xmm0 =
xmm0[0],xmm1[0],xmm0[2,3]
+# CHECK-NEXT: vmovaps %xmm0, -496(%rbp)
+ movaps xmmword ptr [rbp - 496], xmm0
+# CHECK-NEXT: vmovss -252(%rbp), %xmm1
+ movss xmm1, dword ptr [rbp - 252] # xmm1 = mem[0],zero,zero,zero
+# CHECK-NEXT: vmovaps %xmm1, -192(%rbp)
+ movaps xmmword ptr [rbp - 192], xmm1
+# CHECK-NEXT: vdivss %xmm1, %xmm0, %xmm0
+ divss xmm0, xmm1
+# CHECK-NEXT: vmovaps %xmm0, -192(%rbp)
+ movaps xmmword ptr [rbp - 192], xmm0
+# CHECK-NEXT: vmovd -128(%rbp), %xmm0
+ movd xmm0, dword ptr [rbp - 128] # xmm0 = mem[0],zero,zero,zero
+# CHECK-NEXT: vpinsrd $1, %edx, %xmm0, %xmm0
+ pinsrd xmm0, edx, 1
+# CHECK-NEXT: vmovaps %xmm0, -144(%rbp)
+ movaps xmmword ptr [rbp - 144], xmm0
+# CHECK-NEXT: vmovd -160(%rbp), %xmm0
+ movd xmm0, dword ptr [rbp - 160] # xmm0 = mem[0],zero,zero,zero
+# CHECK-NEXT: vpblendw $170, %xmm1, %xmm0, %xmm0 # xmm0 =
xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7]
+ pblendw xmm0, xmm1, 170 # xmm0 =
xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7]
+# CHECK-NEXT: vmovdqa %xmm0, -576(%rbp)
+ movdqa xmmword ptr [rbp - 576], xmm0
+# CHECK-NEXT: vphsubw %xmm1, %xmm0, %xmm0
+ phsubw xmm0, xmm1
+# CHECK-NEXT: vmovdqa %xmm0, -592(%rbp)
+ movdqa xmmword ptr [rbp - 592], xmm0
+# CHECK-NEXT: vmovaps -496(%rbp), %xmm0
+ movaps xmm0, xmmword ptr [rbp - 496]
+# CHECK-NEXT: vroundps $8, %xmm0, %xmm0
+ roundps xmm0, xmm0, 8
+# CHECK-NEXT: vmovaps %xmm0, -608(%rbp)
+ movaps xmmword ptr [rbp - 608], xmm0
+# CHECK-NEXT: vmovapd -432(%rbp), %xmm0
+ movapd xmm0, xmmword ptr [rbp - 432]
+# CHECK-NEXT: vpxor %xmm1, %xmm0, %xmm0
+ pxor xmm0, xmm1
+# CHECK-NEXT: vmovaps %xmm0, -640(%rbp)
+ movaps xmmword ptr [rbp - 640], xmm0
+# CHECK-NEXT: vmovapd %xmm0, -32(%rbp)
+ movapd xmmword ptr [rbp - 32], xmm0
+# CHECK-NEXT: vmovupd %xmm0, (%rax)
+ movupd xmmword ptr [rax], xmm0
+# CHECK-NEXT: vmovsd -656(%rbp), %xmm0
+ movsd xmm0, qword ptr [rbp - 656] # xmm0 = mem[0],zero
+# CHECK-NEXT: extrq $8, $16, %xmm0 # xmm0 =
xmm0[1,2],zero,zero,zero,zero,zero,zero,xmm0[u,u,u,u,u,u,u,u]
+ extrq xmm0, 16, 8
+# CHECK-NEXT: insertq $8, $16, %xmm1, %xmm0 # xmm0 =
xmm0[0],xmm1[0,1],xmm0[3,4,5,6,7,u,u,u,u,u,u,u,u]
+ insertq xmm0, xmm1, 16, 8
+# CHECK-NEXT: pshufw $1, %mm0, %mm2 # mm2 = mm0[1,0,0,0]
+ pshufw mm2, mm0, 1
>From 8f2a402acd8aeede670d35e16159d31596363c37 Mon Sep 17 00:00:00 2001
From: Chauhan Jaydeep Ashwinbhai <chauhan.jaydeep.ashwinb...@intel.com>
Date: Fri, 28 Jun 2024 23:40:30 +0800
Subject: [PATCH 04/14] Moved replaceSSE2AVXOpcode inside
X86AsmParser::processInstruction
---
.../lib/Target/X86/AsmParser/X86AsmParser.cpp | 36 ++++++++-----------
llvm/test/MC/AsmParser/sse2avx-intel.s | 4 +--
2 files changed, 17 insertions(+), 23 deletions(-)
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index 644ed451cb18e..304758ad989d1 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -3749,7 +3749,22 @@ bool X86AsmParser::ParseInstruction(ParseInstructionInfo
&Info, StringRef Name,
return false;
}
+void replaceSSE2AVXOpcode(MCInst &Inst) {
+ ArrayRef<X86TableEntry> Table{X86SSE2AVXTable};
+ unsigned Opcode = Inst.getOpcode();
+ const auto I = llvm::lower_bound(Table, Opcode);
+ if (I != Table.end() && I->OldOpc == Opcode) {
+ Inst.setOpcode(I->NewOpc);
+ }
+}
+
bool X86AsmParser::processInstruction(MCInst &Inst, const OperandVector &Ops) {
+ // When "-msse2avx" option is enabled replaceSSE2AVXOpcode method will
+ // replace SSE instruction with equivalent AVX instruction using mapping
given
+ // in table GET_X86_SSE2AVX_TABLE
+ if (MCOptions.SSE2AVX)
+ replaceSSE2AVXOpcode(Inst);
+
if (ForcedOpcodePrefix != OpcodePrefix_VEX3 &&
X86::optimizeInstFromVEX3ToVEX2(Inst, MII.get(Inst.getOpcode())))
return true;
@@ -4145,15 +4160,6 @@ unsigned X86AsmParser::checkTargetMatchPredicate(MCInst
&Inst) {
return Match_Success;
}
-void replaceSSE2AVXOpcode(llvm::MCInst &Inst) {
- ArrayRef<X86TableEntry> Table{X86SSE2AVXTable};
- unsigned Opcode = Inst.getOpcode();
- const auto I = llvm::lower_bound(Table, Opcode);
- if (I != Table.end() && I->OldOpc == Opcode) {
- Inst.setOpcode(I->NewOpc);
- }
-}
-
bool X86AsmParser::matchAndEmitATTInstruction(
SMLoc IDLoc, unsigned &Opcode, MCInst &Inst, OperandVector &Operands,
MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm) {
@@ -4173,12 +4179,6 @@ bool X86AsmParser::matchAndEmitATTInstruction(
ForcedDataPrefix = 0;
}
- // When "-msse2avx" option is enabled replaceSSE2AVXOpcode method will
- // replace SSE instruction with equivalent AVX instruction using mapping
given
- // in table GET_X86_SSE2AVX_TABLE
- if (MCOptions.SSE2AVX)
- replaceSSE2AVXOpcode(Inst);
-
switch (OriginalError) {
default: llvm_unreachable("Unexpected match result!");
case Match_Success:
@@ -4513,12 +4513,6 @@ bool X86AsmParser::matchAndEmitIntelInstruction(
/*Len=*/0, UnsizedMemOp->getMemFrontendSize());
}
- // When "-msse2avx" option is enabled replaceSSE2AVXOpcode method will
- // replace SSE instruction with equivalent AVX instruction using mapping
given
- // in table GET_X86_SSE2AVX_TABLE
- if (MCOptions.SSE2AVX)
- replaceSSE2AVXOpcode(Inst);
-
// If exactly one matched, then we treat that as a successful match (and the
// instruction will already have been filled in correctly, since the failing
// matches won't have modified it).
diff --git a/llvm/test/MC/AsmParser/sse2avx-intel.s
b/llvm/test/MC/AsmParser/sse2avx-intel.s
index 72f3638a41a81..11d25089c250a 100644
--- a/llvm/test/MC/AsmParser/sse2avx-intel.s
+++ b/llvm/test/MC/AsmParser/sse2avx-intel.s
@@ -16,7 +16,7 @@
unpcklpd xmm0, xmm1 # xmm0 = xmm0[0],xmm1[0]
# CHECK-NEXT: vaddpd %xmm1, %xmm0, %xmm0
addpd xmm0, xmm1
-# CHECK-NEXT: vmovapd %xmm0, -464(%rbp)
+# CHECK-NEXT: vmovapd %xmm0, -464(%rbp)
movapd xmmword ptr [rbp - 464], xmm0
# CHECK-NEXT: vmovaps -304(%rbp), %xmm1
movaps xmm1, xmmword ptr [rbp - 304]
@@ -50,7 +50,7 @@
pblendw xmm0, xmm1, 170 # xmm0 =
xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7]
# CHECK-NEXT: vmovdqa %xmm0, -576(%rbp)
movdqa xmmword ptr [rbp - 576], xmm0
-# CHECK-NEXT: vphsubw %xmm1, %xmm0, %xmm0
+# CHECK-NEXT: vphsubw %xmm1, %xmm0, %xmm0
phsubw xmm0, xmm1
# CHECK-NEXT: vmovdqa %xmm0, -592(%rbp)
movdqa xmmword ptr [rbp - 592], xmm0
>From c90119457e7c71167bdaf3f319ba8015b5cabd34 Mon Sep 17 00:00:00 2001
From: Chauhan Jaydeep Ashwinbhai <chauhan.jaydeep.ashwinb...@intel.com>
Date: Sat, 29 Jun 2024 19:35:09 +0800
Subject: [PATCH 05/14] Addressed review comments
---
llvm/include/llvm/MC/MCTargetOptions.h | 3 ++-
llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp | 6 ++----
llvm/test/MC/AsmParser/sse2avx-intel.s | 2 +-
llvm/test/MC/AsmParser/sse2avx.s | 2 +-
4 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/llvm/include/llvm/MC/MCTargetOptions.h
b/llvm/include/llvm/MC/MCTargetOptions.h
index 90fe356d47077..8ac96c64f0786 100644
--- a/llvm/include/llvm/MC/MCTargetOptions.h
+++ b/llvm/include/llvm/MC/MCTargetOptions.h
@@ -55,7 +55,6 @@ class MCTargetOptions {
bool ShowMCEncoding : 1;
bool ShowMCInst : 1;
bool AsmVerbose : 1;
- bool SSE2AVX : 1;
/// Preserve Comments in Assembly.
bool PreserveAsmComments : 1;
@@ -66,6 +65,8 @@ class MCTargetOptions {
// ELF.
bool X86RelaxRelocations = true;
+ bool SSE2AVX : 1;
+
EmitDwarfUnwindType EmitDwarfUnwind;
int DwarfVersion = 0;
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index 304758ad989d1..c425067e085ce 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -3749,13 +3749,12 @@ bool
X86AsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
return false;
}
-void replaceSSE2AVXOpcode(MCInst &Inst) {
+static void replaceSSE2AVXOpcode(MCInst &Inst) {
ArrayRef<X86TableEntry> Table{X86SSE2AVXTable};
unsigned Opcode = Inst.getOpcode();
const auto I = llvm::lower_bound(Table, Opcode);
- if (I != Table.end() && I->OldOpc == Opcode) {
+ if (I != Table.end() && I->OldOpc == Opcode)
Inst.setOpcode(I->NewOpc);
- }
}
bool X86AsmParser::processInstruction(MCInst &Inst, const OperandVector &Ops) {
@@ -4178,7 +4177,6 @@ bool X86AsmParser::matchAndEmitATTInstruction(
SwitchMode(X86::Is16Bit);
ForcedDataPrefix = 0;
}
-
switch (OriginalError) {
default: llvm_unreachable("Unexpected match result!");
case Match_Success:
diff --git a/llvm/test/MC/AsmParser/sse2avx-intel.s
b/llvm/test/MC/AsmParser/sse2avx-intel.s
index 11d25089c250a..69198e0ca42ce 100644
--- a/llvm/test/MC/AsmParser/sse2avx-intel.s
+++ b/llvm/test/MC/AsmParser/sse2avx-intel.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel -msse2avx
%s | FileCheck %s
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -msse2avx %s | FileCheck %s
.text
# CHECK: vmovsd -352(%rbp), %xmm0
movsd xmm0, qword ptr [rbp - 352] # xmm0 = mem[0],zero
diff --git a/llvm/test/MC/AsmParser/sse2avx.s b/llvm/test/MC/AsmParser/sse2avx.s
index 29f2181dfcce8..a21ca6529cabd 100644
--- a/llvm/test/MC/AsmParser/sse2avx.s
+++ b/llvm/test/MC/AsmParser/sse2avx.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -triple x86_64-unknown-unknown -msse2avx %s | FileCheck %s
+# RUN: llvm-mc -triple x86_64 -msse2avx %s | FileCheck %s
.text
# CHECK: vmovsd -352(%rbp), %xmm0
movsd -352(%rbp), %xmm0 # xmm0 = mem[0],zero
>From 3623d8d0693009c2b8121fcc11fb2420dd46bed8 Mon Sep 17 00:00:00 2001
From: Chauhan Jaydeep Ashwinbhai <chauhan.jaydeep.ashwinb...@intel.com>
Date: Mon, 1 Jul 2024 20:55:59 +0800
Subject: [PATCH 06/14] Added support for instructions
BLENDVPD,BLENDVPS,PBLENDVB
---
llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp | 6 ++++++
llvm/test/MC/AsmParser/sse2avx.s | 6 ++++++
llvm/utils/TableGen/X86InstrMappingEmitter.cpp | 3 +++
3 files changed, 15 insertions(+)
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index c425067e085ce..8212adee4574d 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -3755,6 +3755,12 @@ static void replaceSSE2AVXOpcode(MCInst &Inst) {
const auto I = llvm::lower_bound(Table, Opcode);
if (I != Table.end() && I->OldOpc == Opcode)
Inst.setOpcode(I->NewOpc);
+
+ if (X86::isBLENDVPD(Opcode) || X86::isBLENDVPS(Opcode) ||
+ X86::isPBLENDVB(Opcode)) {
+ unsigned RegNo = Inst.getOperand(2).getReg();
+ Inst.addOperand(MCOperand::createReg(RegNo));
+ }
}
bool X86AsmParser::processInstruction(MCInst &Inst, const OperandVector &Ops) {
diff --git a/llvm/test/MC/AsmParser/sse2avx.s b/llvm/test/MC/AsmParser/sse2avx.s
index a21ca6529cabd..e514ece1a2613 100644
--- a/llvm/test/MC/AsmParser/sse2avx.s
+++ b/llvm/test/MC/AsmParser/sse2avx.s
@@ -78,3 +78,9 @@
insertq $16, $8, %xmm1, %xmm0
# CHECK-NEXT: pshufw $1, %mm0, %mm2 # mm2 = mm0[1,0,0,0]
pshufw $1, %mm0, %mm2
+# CHECK-NEXT: vpblendvb %xmm2, %xmm2, %xmm1, %xmm1
+ pblendvb %xmm0, %xmm2, %xmm1
+# CHECK-NEXT: vblendvps %xmm0, %xmm0, %xmm2, %xmm2
+ blendvps %xmm0, %xmm0, %xmm2
+# CHECK-NEXT: vblendvpd %xmm0, %xmm0, %xmm2, %xmm2
+ blendvpd %xmm0, %xmm0, %xmm2
diff --git a/llvm/utils/TableGen/X86InstrMappingEmitter.cpp
b/llvm/utils/TableGen/X86InstrMappingEmitter.cpp
index 90611de641f30..e8039db11d784 100644
--- a/llvm/utils/TableGen/X86InstrMappingEmitter.cpp
+++ b/llvm/utils/TableGen/X86InstrMappingEmitter.cpp
@@ -350,6 +350,9 @@ void X86InstrMappingEmitter::emitSSE2AVXTable(
continue;
std::string NewName = ("V" + Name).str();
+ // Handle instructions BLENDVPD, BLENDVPS ,PBLENDVB
+ if (Name.ends_with("rm0") || Name.ends_with("rr0"))
+ NewName.back() = 'r';
auto *AVXRec = Records.getDef(NewName);
if (!AVXRec)
continue;
>From 6ca47cd9ecfa615d41085726594a44293622e4d8 Mon Sep 17 00:00:00 2001
From: Chauhan Jaydeep Ashwinbhai <chauhan.jaydeep.ashwinb...@intel.com>
Date: Tue, 2 Jul 2024 12:39:26 +0800
Subject: [PATCH 07/14] Added test for blendvpd instruction
---
llvm/test/MC/AsmParser/sse2avx.s | 2 ++
1 file changed, 2 insertions(+)
diff --git a/llvm/test/MC/AsmParser/sse2avx.s b/llvm/test/MC/AsmParser/sse2avx.s
index e514ece1a2613..d63b79879b07b 100644
--- a/llvm/test/MC/AsmParser/sse2avx.s
+++ b/llvm/test/MC/AsmParser/sse2avx.s
@@ -84,3 +84,5 @@
blendvps %xmm0, %xmm0, %xmm2
# CHECK-NEXT: vblendvpd %xmm0, %xmm0, %xmm2, %xmm2
blendvpd %xmm0, %xmm0, %xmm2
+# CHECK-NEXT: vblendvpd %xmm0, %xmm0, %xmm2, %xmm2
+ blendvpd %xmm0, %xmm2
>From b0cca0e7e50ab786a9ed3853e9f1b07afdbec7f5 Mon Sep 17 00:00:00 2001
From: Chauhan Jaydeep Ashwinbhai <chauhan.jaydeep.ashwinb...@intel.com>
Date: Wed, 3 Jul 2024 23:34:53 +0800
Subject: [PATCH 08/14] Changed SSE2AVX option to bool and sync intel test
---
llvm/include/llvm/MC/MCTargetOptions.h | 2 +-
llvm/lib/MC/MCTargetOptions.cpp | 2 +-
llvm/test/MC/AsmParser/sse2avx-intel.s | 8 ++++++++
3 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/llvm/include/llvm/MC/MCTargetOptions.h
b/llvm/include/llvm/MC/MCTargetOptions.h
index 25d4dcbf21b5f..a6bf0841c6428 100644
--- a/llvm/include/llvm/MC/MCTargetOptions.h
+++ b/llvm/include/llvm/MC/MCTargetOptions.h
@@ -68,7 +68,7 @@ class MCTargetOptions {
// ELF.
bool X86RelaxRelocations = true;
- bool SSE2AVX : 1;
+ bool SSE2AVX = false;
EmitDwarfUnwindType EmitDwarfUnwind;
diff --git a/llvm/lib/MC/MCTargetOptions.cpp b/llvm/lib/MC/MCTargetOptions.cpp
index 227d9fc347e71..bff4b8da2fb1b 100644
--- a/llvm/lib/MC/MCTargetOptions.cpp
+++ b/llvm/lib/MC/MCTargetOptions.cpp
@@ -16,7 +16,7 @@ MCTargetOptions::MCTargetOptions()
MCNoWarn(false), MCNoDeprecatedWarn(false), MCNoTypeCheck(false),
MCSaveTempLabels(false), MCIncrementalLinkerCompatible(false),
FDPIC(false), ShowMCEncoding(false), ShowMCInst(false),
AsmVerbose(false),
- SSE2AVX(false), PreserveAsmComments(true), Dwarf64(false),
+ PreserveAsmComments(true), Dwarf64(false),
EmitDwarfUnwind(EmitDwarfUnwindType::Default),
MCUseDwarfDirectory(DefaultDwarfDirectory),
EmitCompactUnwindNonCanonical(false), PPCUseFullRegisterNames(false) {}
diff --git a/llvm/test/MC/AsmParser/sse2avx-intel.s
b/llvm/test/MC/AsmParser/sse2avx-intel.s
index 69198e0ca42ce..832313a1d1ee2 100644
--- a/llvm/test/MC/AsmParser/sse2avx-intel.s
+++ b/llvm/test/MC/AsmParser/sse2avx-intel.s
@@ -78,3 +78,11 @@
insertq xmm0, xmm1, 16, 8
# CHECK-NEXT: pshufw $1, %mm0, %mm2 # mm2 = mm0[1,0,0,0]
pshufw mm2, mm0, 1
+# CHECK-NEXT: vpblendvb %xmm2, %xmm2, %xmm1, %xmm1
+ pblendvb xmm1, xmm2, xmm0
+# CHECK-NEXT: vblendvps %xmm0, %xmm0, %xmm2, %xmm2
+ blendvps xmm2, xmm0, xmm0
+# CHECK-NEXT: vblendvpd %xmm0, %xmm0, %xmm2, %xmm2
+ blendvpd xmm2, xmm0, xmm0
+# CHECK-NEXT: vblendvpd %xmm0, %xmm0, %xmm2, %xmm2
+ blendvpd xmm2, xmm0
>From b62d52dd9e13fc85de48c802b316f1ba99749079 Mon Sep 17 00:00:00 2001
From: Chauhan Jaydeep Ashwinbhai <chauhan.jaydeep.ashwinb...@intel.com>
Date: Tue, 9 Jul 2024 01:21:59 +0800
Subject: [PATCH 09/14] Added -msse2avx as clang and -x86-sse2avx as llvm-mc
options
---
clang/include/clang/Basic/CodeGenOptions.def | 1 +
clang/include/clang/Driver/Options.td | 5 ++
clang/lib/Driver/ToolChains/Clang.cpp | 3 +
clang/tools/driver/cc1as_main.cpp | 5 ++
llvm/include/llvm/MC/MCTargetOptions.h | 2 +-
.../llvm/MC/MCTargetOptionsCommandFlags.h | 4 +-
llvm/lib/MC/MCTargetOptionsCommandFlags.cpp | 12 +--
.../lib/Target/X86/AsmParser/X86AsmParser.cpp | 2 +-
llvm/test/MC/AsmParser/sse2avx-clang.s | 89 +++++++++++++++++++
llvm/test/MC/AsmParser/sse2avx-intel.s | 2 +-
llvm/test/MC/AsmParser/sse2avx.s | 2 +-
11 files changed, 115 insertions(+), 12 deletions(-)
create mode 100644 llvm/test/MC/AsmParser/sse2avx-clang.s
diff --git a/clang/include/clang/Basic/CodeGenOptions.def
b/clang/include/clang/Basic/CodeGenOptions.def
index 25de2204f04c0..68ddfa68a8d7d 100644
--- a/clang/include/clang/Basic/CodeGenOptions.def
+++ b/clang/include/clang/Basic/CodeGenOptions.def
@@ -38,6 +38,7 @@ VALUE_CODEGENOPT(Name, Bits, Default)
CODEGENOPT(DisableIntegratedAS, 1, 0) ///< -no-integrated-as
CODEGENOPT(Crel, 1, 0) ///< -Wa,--crel
CODEGENOPT(RelaxELFRelocations, 1, 1) ///< -Wa,-mrelax-relocations={yes,no}
+CODEGENOPT(SSE2AVX , 1, 0) ///< -msse2avx
CODEGENOPT(AsmVerbose , 1, 0) ///< -dA, -fverbose-asm.
CODEGENOPT(PreserveAsmComments, 1, 1) ///< -dA, -fno-preserve-as-comments.
CODEGENOPT(AssumeSaneOperatorNew , 1, 1) ///< implicit __attribute__((malloc))
operator new
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 58ca6f2bea9e4..adb477f4bcbb3 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -4761,6 +4761,7 @@ def mno_tls_direct_seg_refs : Flag<["-"],
"mno-tls-direct-seg-refs">, Group<m_Gr
HelpText<"Disable direct TLS access through segment registers">,
MarshallingInfoFlag<CodeGenOpts<"IndirectTlsSegRefs">>;
def mno_relax_all : Flag<["-"], "mno-relax-all">, Group<m_Group>;
+def mno_sse2avx : Flag<["-"], "mno-sse2avx">, Group<m_Group>;
let Flags = [TargetSpecific] in {
def mno_rtd: Flag<["-"], "mno-rtd">, Group<m_Group>;
def mno_soft_float : Flag<["-"], "mno-soft-float">, Group<m_Group>;
@@ -5186,6 +5187,10 @@ def mrelax_all : Flag<["-"], "mrelax-all">,
Group<m_Group>,
Visibility<[ClangOption, CC1Option, CC1AsOption]>,
HelpText<"(integrated-as) Relax all machine instructions">,
MarshallingInfoFlag<CodeGenOpts<"RelaxAll">>;
+def msse2avx : Flag<["-"], "msse2avx">, Group<m_Group>,
+ Visibility<[ClangOption, CC1Option, CC1AsOption]>,
+ HelpText<"Convert SSE to AVX Instructions">,
+ MarshallingInfoFlag<CodeGenOpts<"SSE2AVX">>;
def mincremental_linker_compatible : Flag<["-"],
"mincremental-linker-compatible">, Group<m_Group>,
Visibility<[ClangOption, CC1Option, CC1AsOption]>,
HelpText<"(integrated-as) Emit an object file which can be used with an
incremental linker">,
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp
b/clang/lib/Driver/ToolChains/Clang.cpp
index aa285c39f14b4..e3ea1488a4629 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -8359,6 +8359,9 @@ void ClangAs::AddX86TargetArgs(const ArgList &Args,
addX86AlignBranchArgs(getToolChain().getDriver(), Args, CmdArgs,
/*IsLTO=*/false);
+ if (Args.hasFlag(options::OPT_msse2avx, options::OPT_mno_sse2avx, true))
+ Args.addOptInFlag(CmdArgs, options::OPT_msse2avx,
options::OPT_mno_sse2avx);
+
if (Arg *A = Args.getLastArg(options::OPT_masm_EQ)) {
StringRef Value = A->getValue();
if (Value == "intel" || Value == "att") {
diff --git a/clang/tools/driver/cc1as_main.cpp
b/clang/tools/driver/cc1as_main.cpp
index 4e0aa1450563e..ec93f092713f5 100644
--- a/clang/tools/driver/cc1as_main.cpp
+++ b/clang/tools/driver/cc1as_main.cpp
@@ -98,6 +98,8 @@ struct AssemblerInvocation {
LLVM_PREFERRED_TYPE(bool)
unsigned RelaxELFRelocations : 1;
LLVM_PREFERRED_TYPE(bool)
+ unsigned SSE2AVX : 1;
+ LLVM_PREFERRED_TYPE(bool)
unsigned Dwarf64 : 1;
unsigned DwarfVersion;
std::string DwarfDebugFlags;
@@ -197,6 +199,7 @@ struct AssemblerInvocation {
ShowInst = 0;
ShowEncoding = 0;
RelaxAll = 0;
+ SSE2AVX = 0;
NoExecStack = 0;
FatalWarnings = 0;
NoWarn = 0;
@@ -288,6 +291,7 @@ bool
AssemblerInvocation::CreateFromArgs(AssemblerInvocation &Opts,
}
Opts.RelaxELFRelocations = !Args.hasArg(OPT_mrelax_relocations_no);
+ Opts.SSE2AVX = Args.hasArg(OPT_msse2avx);
if (auto *DwarfFormatArg = Args.getLastArg(OPT_gdwarf64, OPT_gdwarf32))
Opts.Dwarf64 = DwarfFormatArg->getOption().matches(OPT_gdwarf64);
Opts.DwarfVersion = getLastArgIntValue(Args, OPT_dwarf_version_EQ, 2, Diags);
@@ -437,6 +441,7 @@ static bool ExecuteAssemblerImpl(AssemblerInvocation &Opts,
MCOptions.MCSaveTempLabels = Opts.SaveTemporaryLabels;
MCOptions.Crel = Opts.Crel;
MCOptions.X86RelaxRelocations = Opts.RelaxELFRelocations;
+ MCOptions.X86Sse2Avx = Opts.SSE2AVX;
MCOptions.CompressDebugSections = Opts.CompressDebugSections;
MCOptions.AsSecureLogFile = Opts.AsSecureLogFile;
diff --git a/llvm/include/llvm/MC/MCTargetOptions.h
b/llvm/include/llvm/MC/MCTargetOptions.h
index a6bf0841c6428..899299fd15246 100644
--- a/llvm/include/llvm/MC/MCTargetOptions.h
+++ b/llvm/include/llvm/MC/MCTargetOptions.h
@@ -68,7 +68,7 @@ class MCTargetOptions {
// ELF.
bool X86RelaxRelocations = true;
- bool SSE2AVX = false;
+ bool X86Sse2Avx = false;
EmitDwarfUnwindType EmitDwarfUnwind;
diff --git a/llvm/include/llvm/MC/MCTargetOptionsCommandFlags.h
b/llvm/include/llvm/MC/MCTargetOptionsCommandFlags.h
index b108cdc6e4a65..9d592446f3ba7 100644
--- a/llvm/include/llvm/MC/MCTargetOptionsCommandFlags.h
+++ b/llvm/include/llvm/MC/MCTargetOptionsCommandFlags.h
@@ -41,8 +41,6 @@ bool getEmitCompactUnwindNonCanonical();
bool getShowMCInst();
-bool getSSE2AVX();
-
bool getFatalWarnings();
bool getNoWarn();
@@ -57,6 +55,8 @@ bool getCrel();
bool getX86RelaxRelocations();
+bool getX86Sse2Avx();
+
std::string getABIName();
std::string getAsSecureLogFile();
diff --git a/llvm/lib/MC/MCTargetOptionsCommandFlags.cpp
b/llvm/lib/MC/MCTargetOptionsCommandFlags.cpp
index fb7a72d4d0073..813cebbc07bde 100644
--- a/llvm/lib/MC/MCTargetOptionsCommandFlags.cpp
+++ b/llvm/lib/MC/MCTargetOptionsCommandFlags.cpp
@@ -42,7 +42,6 @@ MCOPT(bool, Dwarf64)
MCOPT(EmitDwarfUnwindType, EmitDwarfUnwind)
MCOPT(bool, EmitCompactUnwindNonCanonical)
MCOPT(bool, ShowMCInst)
-MCOPT(bool, SSE2AVX)
MCOPT(bool, FatalWarnings)
MCOPT(bool, NoWarn)
MCOPT(bool, NoDeprecatedWarn)
@@ -50,6 +49,7 @@ MCOPT(bool, NoTypeCheck)
MCOPT(bool, SaveTempLabels)
MCOPT(bool, Crel)
MCOPT(bool, X86RelaxRelocations)
+MCOPT(bool, X86Sse2Avx)
MCOPT(std::string, ABIName)
MCOPT(std::string, AsSecureLogFile)
@@ -109,10 +109,6 @@
llvm::mc::RegisterMCTargetOptionsFlags::RegisterMCTargetOptionsFlags() {
cl::desc("Emit internal instruction representation to assembly file"));
MCBINDOPT(ShowMCInst);
- static cl::opt<bool> SSE2AVX(
- "msse2avx", cl::desc("Convert SSE Instructions to AVX Instructions"));
- MCBINDOPT(SSE2AVX);
-
static cl::opt<bool> FatalWarnings("fatal-warnings",
cl::desc("Treat warnings as errors"));
MCBINDOPT(FatalWarnings);
@@ -145,6 +141,10 @@
llvm::mc::RegisterMCTargetOptionsFlags::RegisterMCTargetOptionsFlags() {
cl::init(true));
MCBINDOPT(X86RelaxRelocations);
+ static cl::opt<bool> X86Sse2Avx(
+ "x86-sse2avx", cl::desc("Convert SSE Instructions to AVX Instructions"));
+ MCBINDOPT(X86Sse2Avx);
+
static cl::opt<std::string> ABIName(
"target-abi", cl::Hidden,
cl::desc("The name of the ABI to be targeted from the backend."),
@@ -166,7 +166,6 @@ MCTargetOptions llvm::mc::InitMCTargetOptionsFromFlags() {
Options.Dwarf64 = getDwarf64();
Options.DwarfVersion = getDwarfVersion();
Options.ShowMCInst = getShowMCInst();
- Options.SSE2AVX = getSSE2AVX();
Options.ABIName = getABIName();
Options.MCFatalWarnings = getFatalWarnings();
Options.MCNoWarn = getNoWarn();
@@ -175,6 +174,7 @@ MCTargetOptions llvm::mc::InitMCTargetOptionsFromFlags() {
Options.MCSaveTempLabels = getSaveTempLabels();
Options.Crel = getCrel();
Options.X86RelaxRelocations = getX86RelaxRelocations();
+ Options.X86Sse2Avx = getX86Sse2Avx();
Options.EmitDwarfUnwind = getEmitDwarfUnwind();
Options.EmitCompactUnwindNonCanonical = getEmitCompactUnwindNonCanonical();
Options.AsSecureLogFile = getAsSecureLogFile();
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index e3a952adc7c4b..f24fb393a304f 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -3767,7 +3767,7 @@ bool X86AsmParser::processInstruction(MCInst &Inst, const
OperandVector &Ops) {
// When "-msse2avx" option is enabled replaceSSE2AVXOpcode method will
// replace SSE instruction with equivalent AVX instruction using mapping
given
// in table GET_X86_SSE2AVX_TABLE
- if (MCOptions.SSE2AVX)
+ if (MCOptions.X86Sse2Avx)
replaceSSE2AVXOpcode(Inst);
if (ForcedOpcodePrefix != OpcodePrefix_VEX3 &&
diff --git a/llvm/test/MC/AsmParser/sse2avx-clang.s
b/llvm/test/MC/AsmParser/sse2avx-clang.s
new file mode 100644
index 0000000000000..ae351adfc4b65
--- /dev/null
+++ b/llvm/test/MC/AsmParser/sse2avx-clang.s
@@ -0,0 +1,89 @@
+# RUN: clang -march=x86-64 -msse2avx %s -c -o %t
+# RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck %s
+
+# CHECK: 0: vmovsd -0x160(%rbp), %xmm0
+ movsd -352(%rbp), %xmm0 # xmm0 = mem[0],zero
+# CHECK-NEXT: 8: vunpcklpd %xmm1, %xmm0, %xmm0 # xmm0 =
xmm0[0],xmm1[0]
+ unpcklpd %xmm1, %xmm0 # xmm0 =
xmm0[0],xmm1[0]
+# CHECK-NEXT: c: vmovapd %xmm0, -0x170(%rbp)
+ movapd %xmm0, -368(%rbp)
+# CHECK-NEXT: 14: vmovapd -0x170(%rbp), %xmm0
+ movapd -368(%rbp), %xmm0
+# CHECK-NEXT: 1c: vmovsd -0x178(%rbp), %xmm1
+ movsd -376(%rbp), %xmm1 # xmm1 = mem[0],zero
+# CHECK-NEXT: 24: vmovsd -0x180(%rbp), %xmm0
+ movsd -384(%rbp), %xmm0 # xmm0 = mem[0],zero
+# CHECK-NEXT: 2c: vunpcklpd %xmm1, %xmm0, %xmm0 # xmm0 =
xmm0[0],xmm1[0]
+ unpcklpd %xmm1, %xmm0 # xmm0 =
xmm0[0],xmm1[0]
+# CHECK-NEXT: 30: vaddpd %xmm1, %xmm0, %xmm0
+ addpd %xmm1, %xmm0
+# CHECK-NEXT: 34: vmovapd %xmm0, -0x1d0(%rbp)
+ movapd %xmm0, -464(%rbp)
+# CHECK-NEXT: 3c: vmovaps -0x130(%rbp), %xmm1
+ movaps -304(%rbp), %xmm1
+# CHECK-NEXT: 44: vpandn %xmm1, %xmm0, %xmm0
+ pandn %xmm1, %xmm0
+# CHECK-NEXT: 48: vmovaps %xmm0, -0x1e0(%rbp)
+ movaps %xmm0, -480(%rbp)
+# CHECK-NEXT: 50: vmovss -0xdc(%rbp), %xmm1
+ movss -220(%rbp), %xmm1 # xmm1 = mem[0],zero,zero,zero
+# CHECK-NEXT: 58: vinsertps $0x10, %xmm1, %xmm0, %xmm0 # xmm0
= xmm0[0],xmm1[0],xmm0[2,3]
+ insertps $16, %xmm1, %xmm0 # xmm0 =
xmm0[0],xmm1[0]
+# CHECK-NEXT: 5e: vmovaps %xmm0, -0x1f0(%rbp)
+ movaps %xmm0, -496(%rbp)
+# CHECK-NEXT: 66: vmovss -0x100(%rbp), %xmm0
+ movss -256(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
+# CHECK-NEXT: 6e: vmovaps -0xc0(%rbp), %xmm0
+ movaps -192(%rbp), %xmm0
+# CHECK-NEXT: 76: vdivss %xmm1, %xmm0, %xmm0
+ divss %xmm1, %xmm0
+# CHECK-NEXT: 7a: vmovaps %xmm0, -0xc0(%rbp)
+ movaps %xmm0, -192(%rbp)
+# CHECK-NEXT: 82: vmovd -0x80(%rbp), %xmm0
+ movd -128(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
+# CHECK-NEXT: 87: vpinsrd $0x1, %edx, %xmm0, %xmm0
+ pinsrd $1, %edx, %xmm0
+# CHECK-NEXT: 8d: vmovaps %xmm0, -0x90(%rbp)
+ movaps %xmm0, -144(%rbp)
+# CHECK-NEXT: 95: vmovd -0xa0(%rbp), %xmm0
+ movd -160(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
+# CHECK-NEXT: 9d: vpblendw $0xaa, %xmm1, %xmm0, %xmm0 # xmm0
= xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7]
+ pblendw $170, %xmm1, %xmm0 # xmm0 =
xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7]
+# CHECK-NEXT: a3: vmovdqa %xmm0, -0x240(%rbp)
+ movdqa %xmm0, -576(%rbp)
+# CHECK-NEXT: ab: vphsubw %xmm1, %xmm0, %xmm0
+ phsubw %xmm1, %xmm0
+# CHECK-NEXT: b0: vmovdqa %xmm0, -0x250(%rbp)
+ movdqa %xmm0, -592(%rbp)
+# CHECK-NEXT: b8: vmovaps -0x1f0(%rbp), %xmm0
+ movaps -496(%rbp), %xmm0
+# CHECK-NEXT: c0: vroundps $0x8, %xmm0, %xmm0
+ roundps $8, %xmm0, %xmm0
+# CHECK-NEXT: c6: vmovaps %xmm0, -0x260(%rbp)
+ movaps %xmm0, -608(%rbp)
+# CHECK-NEXT: ce: vmovapd -0x1b0(%rbp), %xmm0
+ movapd -432(%rbp), %xmm0
+# CHECK-NEXT: d6: vpxor %xmm1, %xmm0, %xmm0
+ pxor %xmm1, %xmm0
+# CHECK-NEXT: da: vmovaps %xmm0, -0x280(%rbp)
+ movaps %xmm0, -640(%rbp)
+# CHECK-NEXT: e2: vmovapd -0x20(%rbp), %xmm0
+ movapd -32(%rbp), %xmm0
+# CHECK-NEXT: e7: vmovupd %xmm0, (%rax)
+ movupd %xmm0, (%rax)
+# CHECK-NEXT: eb: vmovsd -0x290(%rbp), %xmm0
+ movsd -656(%rbp), %xmm0 # xmm0 = mem[0],zero
+# CHECK-NEXT: f3: extrq $0x10, $0x8, %xmm0 # xmm0 =
xmm0[2],zero,zero,zero,zero,zero,zero,zero,xmm0[u,u,u,u,u,u,u,u]
+ extrq $16, $8, %xmm0
+# CHECK-NEXT: f9: insertq $0x10, $0x8, %xmm1, %xmm0 # xmm0 =
xmm0[0,1],xmm1[0],xmm0[3,4,5,6,7,u,u,u,u,u,u,u,u]
+ insertq $16, $8, %xmm1, %xmm0
+# CHECK-NEXT: ff: pshufw $0x1, %mm0, %mm2 # mm2 =
mm0[1,0,0,0]
+ pshufw $1, %mm0, %mm2
+# CHECK-NEXT: 103: vpblendvb %xmm2, %xmm2, %xmm1, %xmm1
+ pblendvb %xmm0, %xmm2, %xmm1
+# CHECK-NEXT: 109: vblendvps %xmm0, %xmm0, %xmm2, %xmm2
+ blendvps %xmm0, %xmm0, %xmm2
+# CHECK-NEXT: 10f: vblendvpd %xmm0, %xmm0, %xmm2, %xmm2
+ blendvpd %xmm0, %xmm0, %xmm2
+# CHECK-NEXT: 115: vblendvpd %xmm0, %xmm0, %xmm2, %xmm2
+ blendvpd %xmm0, %xmm2
diff --git a/llvm/test/MC/AsmParser/sse2avx-intel.s
b/llvm/test/MC/AsmParser/sse2avx-intel.s
index 832313a1d1ee2..9c8d03863693c 100644
--- a/llvm/test/MC/AsmParser/sse2avx-intel.s
+++ b/llvm/test/MC/AsmParser/sse2avx-intel.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -msse2avx %s | FileCheck %s
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -x86-sse2avx %s |
FileCheck %s
.text
# CHECK: vmovsd -352(%rbp), %xmm0
movsd xmm0, qword ptr [rbp - 352] # xmm0 = mem[0],zero
diff --git a/llvm/test/MC/AsmParser/sse2avx.s b/llvm/test/MC/AsmParser/sse2avx.s
index d63b79879b07b..363529fb7ef27 100644
--- a/llvm/test/MC/AsmParser/sse2avx.s
+++ b/llvm/test/MC/AsmParser/sse2avx.s
@@ -1,4 +1,4 @@
-# RUN: llvm-mc -triple x86_64 -msse2avx %s | FileCheck %s
+# RUN: llvm-mc -triple x86_64 -x86-sse2avx %s | FileCheck %s
.text
# CHECK: vmovsd -352(%rbp), %xmm0
movsd -352(%rbp), %xmm0 # xmm0 = mem[0],zero
>From 7faad7f6e9dcc15e38d9fa95919c4fbf891787a6 Mon Sep 17 00:00:00 2001
From: Chauhan Jaydeep Ashwinbhai <chauhan.jaydeep.ashwinb...@intel.com>
Date: Wed, 10 Jul 2024 18:15:09 +0800
Subject: [PATCH 10/14] Removed -mno-sse2avx option
---
clang/include/clang/Driver/Options.td | 1 -
clang/lib/Driver/ToolChains/Clang.cpp | 4 ++--
.../AsmParser/sse2avx-clang.s => clang/test/Driver/sse2avx.s | 2 +-
3 files changed, 3 insertions(+), 4 deletions(-)
rename llvm/test/MC/AsmParser/sse2avx-clang.s => clang/test/Driver/sse2avx.s
(98%)
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index f6d79a15a2f4f..f5992afdcf595 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -4766,7 +4766,6 @@ def mno_tls_direct_seg_refs : Flag<["-"],
"mno-tls-direct-seg-refs">, Group<m_Gr
HelpText<"Disable direct TLS access through segment registers">,
MarshallingInfoFlag<CodeGenOpts<"IndirectTlsSegRefs">>;
def mno_relax_all : Flag<["-"], "mno-relax-all">, Group<m_Group>;
-def mno_sse2avx : Flag<["-"], "mno-sse2avx">, Group<m_Group>;
let Flags = [TargetSpecific] in {
def mno_rtd: Flag<["-"], "mno-rtd">, Group<m_Group>;
def mno_soft_float : Flag<["-"], "mno-soft-float">, Group<m_Group>;
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp
b/clang/lib/Driver/ToolChains/Clang.cpp
index 8764139f01310..27826f66bf525 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -8362,8 +8362,8 @@ void ClangAs::AddX86TargetArgs(const ArgList &Args,
addX86AlignBranchArgs(getToolChain().getDriver(), Args, CmdArgs,
/*IsLTO=*/false);
- if (Args.hasFlag(options::OPT_msse2avx, options::OPT_mno_sse2avx, true))
- Args.addOptInFlag(CmdArgs, options::OPT_msse2avx,
options::OPT_mno_sse2avx);
+ if (Args.hasArg(options::OPT_msse2avx))
+ Args.AddLastArg(CmdArgs, options::OPT_msse2avx);
if (Arg *A = Args.getLastArg(options::OPT_masm_EQ)) {
StringRef Value = A->getValue();
diff --git a/llvm/test/MC/AsmParser/sse2avx-clang.s
b/clang/test/Driver/sse2avx.s
similarity index 98%
rename from llvm/test/MC/AsmParser/sse2avx-clang.s
rename to clang/test/Driver/sse2avx.s
index ae351adfc4b65..9f574efa83d80 100644
--- a/llvm/test/MC/AsmParser/sse2avx-clang.s
+++ b/clang/test/Driver/sse2avx.s
@@ -1,4 +1,4 @@
-# RUN: clang -march=x86-64 -msse2avx %s -c -o %t
+# RUN: %clang -march=x86-64 -msse2avx %s -c -o %t
# RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck %s
# CHECK: 0: vmovsd -0x160(%rbp), %xmm0
>From 772da90fd30a9558ffe778de3c958ef8efdc797d Mon Sep 17 00:00:00 2001
From: Chauhan Jaydeep Ashwinbhai <chauhan.jaydeep.ashwinb...@intel.com>
Date: Thu, 11 Jul 2024 20:30:16 +0800
Subject: [PATCH 11/14] Addressed review comments
---
clang/lib/Driver/ToolChains/Clang.cpp | 2 +
clang/test/Driver/sse2avx.c | 3 +
clang/test/Driver/sse2avx.s | 90 +--------------------------
3 files changed, 7 insertions(+), 88 deletions(-)
create mode 100644 clang/test/Driver/sse2avx.c
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp
b/clang/lib/Driver/ToolChains/Clang.cpp
index 5eb9547914860..92e49091d31be 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -2708,6 +2708,8 @@ static void CollectArgsForIntegratedAssembler(Compilation
&C,
}
if (!UseRelaxRelocations)
CmdArgs.push_back("-mrelax-relocations=no");
+ if (Args.hasArg(options::OPT_msse2avx))
+ CmdArgs.push_back("-msse2avx");
if (UseNoExecStack)
CmdArgs.push_back("-mnoexecstack");
if (MipsTargetFeature != nullptr) {
diff --git a/clang/test/Driver/sse2avx.c b/clang/test/Driver/sse2avx.c
new file mode 100644
index 0000000000000..da2aa53277fc9
--- /dev/null
+++ b/clang/test/Driver/sse2avx.c
@@ -0,0 +1,3 @@
+// RUN: %clang -### -c -march=x86-64 -msse2avx %s 2>&1 | FileCheck %s
+
+// CHECK: "-msse2avx"
diff --git a/clang/test/Driver/sse2avx.s b/clang/test/Driver/sse2avx.s
index 9f574efa83d80..2277cb5798456 100644
--- a/clang/test/Driver/sse2avx.s
+++ b/clang/test/Driver/sse2avx.s
@@ -1,89 +1,3 @@
-# RUN: %clang -march=x86-64 -msse2avx %s -c -o %t
-# RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck %s
+// RUN: %clang -### -c -march=x86-64 -msse2avx %s 2>&1 | FileCheck %s
-# CHECK: 0: vmovsd -0x160(%rbp), %xmm0
- movsd -352(%rbp), %xmm0 # xmm0 = mem[0],zero
-# CHECK-NEXT: 8: vunpcklpd %xmm1, %xmm0, %xmm0 # xmm0 =
xmm0[0],xmm1[0]
- unpcklpd %xmm1, %xmm0 # xmm0 =
xmm0[0],xmm1[0]
-# CHECK-NEXT: c: vmovapd %xmm0, -0x170(%rbp)
- movapd %xmm0, -368(%rbp)
-# CHECK-NEXT: 14: vmovapd -0x170(%rbp), %xmm0
- movapd -368(%rbp), %xmm0
-# CHECK-NEXT: 1c: vmovsd -0x178(%rbp), %xmm1
- movsd -376(%rbp), %xmm1 # xmm1 = mem[0],zero
-# CHECK-NEXT: 24: vmovsd -0x180(%rbp), %xmm0
- movsd -384(%rbp), %xmm0 # xmm0 = mem[0],zero
-# CHECK-NEXT: 2c: vunpcklpd %xmm1, %xmm0, %xmm0 # xmm0 =
xmm0[0],xmm1[0]
- unpcklpd %xmm1, %xmm0 # xmm0 =
xmm0[0],xmm1[0]
-# CHECK-NEXT: 30: vaddpd %xmm1, %xmm0, %xmm0
- addpd %xmm1, %xmm0
-# CHECK-NEXT: 34: vmovapd %xmm0, -0x1d0(%rbp)
- movapd %xmm0, -464(%rbp)
-# CHECK-NEXT: 3c: vmovaps -0x130(%rbp), %xmm1
- movaps -304(%rbp), %xmm1
-# CHECK-NEXT: 44: vpandn %xmm1, %xmm0, %xmm0
- pandn %xmm1, %xmm0
-# CHECK-NEXT: 48: vmovaps %xmm0, -0x1e0(%rbp)
- movaps %xmm0, -480(%rbp)
-# CHECK-NEXT: 50: vmovss -0xdc(%rbp), %xmm1
- movss -220(%rbp), %xmm1 # xmm1 = mem[0],zero,zero,zero
-# CHECK-NEXT: 58: vinsertps $0x10, %xmm1, %xmm0, %xmm0 # xmm0
= xmm0[0],xmm1[0],xmm0[2,3]
- insertps $16, %xmm1, %xmm0 # xmm0 =
xmm0[0],xmm1[0]
-# CHECK-NEXT: 5e: vmovaps %xmm0, -0x1f0(%rbp)
- movaps %xmm0, -496(%rbp)
-# CHECK-NEXT: 66: vmovss -0x100(%rbp), %xmm0
- movss -256(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
-# CHECK-NEXT: 6e: vmovaps -0xc0(%rbp), %xmm0
- movaps -192(%rbp), %xmm0
-# CHECK-NEXT: 76: vdivss %xmm1, %xmm0, %xmm0
- divss %xmm1, %xmm0
-# CHECK-NEXT: 7a: vmovaps %xmm0, -0xc0(%rbp)
- movaps %xmm0, -192(%rbp)
-# CHECK-NEXT: 82: vmovd -0x80(%rbp), %xmm0
- movd -128(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
-# CHECK-NEXT: 87: vpinsrd $0x1, %edx, %xmm0, %xmm0
- pinsrd $1, %edx, %xmm0
-# CHECK-NEXT: 8d: vmovaps %xmm0, -0x90(%rbp)
- movaps %xmm0, -144(%rbp)
-# CHECK-NEXT: 95: vmovd -0xa0(%rbp), %xmm0
- movd -160(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
-# CHECK-NEXT: 9d: vpblendw $0xaa, %xmm1, %xmm0, %xmm0 # xmm0
= xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7]
- pblendw $170, %xmm1, %xmm0 # xmm0 =
xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7]
-# CHECK-NEXT: a3: vmovdqa %xmm0, -0x240(%rbp)
- movdqa %xmm0, -576(%rbp)
-# CHECK-NEXT: ab: vphsubw %xmm1, %xmm0, %xmm0
- phsubw %xmm1, %xmm0
-# CHECK-NEXT: b0: vmovdqa %xmm0, -0x250(%rbp)
- movdqa %xmm0, -592(%rbp)
-# CHECK-NEXT: b8: vmovaps -0x1f0(%rbp), %xmm0
- movaps -496(%rbp), %xmm0
-# CHECK-NEXT: c0: vroundps $0x8, %xmm0, %xmm0
- roundps $8, %xmm0, %xmm0
-# CHECK-NEXT: c6: vmovaps %xmm0, -0x260(%rbp)
- movaps %xmm0, -608(%rbp)
-# CHECK-NEXT: ce: vmovapd -0x1b0(%rbp), %xmm0
- movapd -432(%rbp), %xmm0
-# CHECK-NEXT: d6: vpxor %xmm1, %xmm0, %xmm0
- pxor %xmm1, %xmm0
-# CHECK-NEXT: da: vmovaps %xmm0, -0x280(%rbp)
- movaps %xmm0, -640(%rbp)
-# CHECK-NEXT: e2: vmovapd -0x20(%rbp), %xmm0
- movapd -32(%rbp), %xmm0
-# CHECK-NEXT: e7: vmovupd %xmm0, (%rax)
- movupd %xmm0, (%rax)
-# CHECK-NEXT: eb: vmovsd -0x290(%rbp), %xmm0
- movsd -656(%rbp), %xmm0 # xmm0 = mem[0],zero
-# CHECK-NEXT: f3: extrq $0x10, $0x8, %xmm0 # xmm0 =
xmm0[2],zero,zero,zero,zero,zero,zero,zero,xmm0[u,u,u,u,u,u,u,u]
- extrq $16, $8, %xmm0
-# CHECK-NEXT: f9: insertq $0x10, $0x8, %xmm1, %xmm0 # xmm0 =
xmm0[0,1],xmm1[0],xmm0[3,4,5,6,7,u,u,u,u,u,u,u,u]
- insertq $16, $8, %xmm1, %xmm0
-# CHECK-NEXT: ff: pshufw $0x1, %mm0, %mm2 # mm2 =
mm0[1,0,0,0]
- pshufw $1, %mm0, %mm2
-# CHECK-NEXT: 103: vpblendvb %xmm2, %xmm2, %xmm1, %xmm1
- pblendvb %xmm0, %xmm2, %xmm1
-# CHECK-NEXT: 109: vblendvps %xmm0, %xmm0, %xmm2, %xmm2
- blendvps %xmm0, %xmm0, %xmm2
-# CHECK-NEXT: 10f: vblendvpd %xmm0, %xmm0, %xmm2, %xmm2
- blendvpd %xmm0, %xmm0, %xmm2
-# CHECK-NEXT: 115: vblendvpd %xmm0, %xmm0, %xmm2, %xmm2
- blendvpd %xmm0, %xmm2
+// CHECK: "-msse2avx"
>From b08971d6504740b4e723626c15106dbfd9661ca5 Mon Sep 17 00:00:00 2001
From: Chauhan Jaydeep Ashwinbhai <chauhan.jaydeep.ashwinb...@intel.com>
Date: Thu, 11 Jul 2024 21:51:45 +0800
Subject: [PATCH 12/14] Addressed review comments
---
clang/include/clang/Driver/Options.td | 2 +-
llvm/test/MC/AsmParser/{sse2avx.s => sse2avx-att.s} | 0
2 files changed, 1 insertion(+), 1 deletion(-)
rename llvm/test/MC/AsmParser/{sse2avx.s => sse2avx-att.s} (100%)
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index ecdaa0246a4f6..c295c72085a45 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -5203,7 +5203,7 @@ def mrelax_all : Flag<["-"], "mrelax-all">,
Group<m_Group>,
MarshallingInfoFlag<CodeGenOpts<"RelaxAll">>;
def msse2avx : Flag<["-"], "msse2avx">, Group<m_Group>,
Visibility<[ClangOption, CC1Option, CC1AsOption]>,
- HelpText<"Convert SSE to AVX Instructions">,
+ HelpText<"Specify that the assembler should encode SSE instructions with VEX
prefix">,
MarshallingInfoFlag<CodeGenOpts<"SSE2AVX">>;
def mincremental_linker_compatible : Flag<["-"],
"mincremental-linker-compatible">, Group<m_Group>,
Visibility<[ClangOption, CC1Option, CC1AsOption]>,
diff --git a/llvm/test/MC/AsmParser/sse2avx.s
b/llvm/test/MC/AsmParser/sse2avx-att.s
similarity index 100%
rename from llvm/test/MC/AsmParser/sse2avx.s
rename to llvm/test/MC/AsmParser/sse2avx-att.s
>From d6916eb2a124f09793815bfa15af0ab978379368 Mon Sep 17 00:00:00 2001
From: Chauhan Jaydeep Ashwinbhai <chauhan.jaydeep.ashwinb...@intel.com>
Date: Fri, 12 Jul 2024 02:27:45 +0800
Subject: [PATCH 13/14] Added mapping of BLENDVPD, BLENDVPS ,PBLENDVB in
X86ManualInstrMapping.def
---
llvm/utils/TableGen/X86InstrMappingEmitter.cpp | 17 ++++++++++++-----
llvm/utils/TableGen/X86ManualInstrMapping.def | 11 +++++++++++
2 files changed, 23 insertions(+), 5 deletions(-)
diff --git a/llvm/utils/TableGen/X86InstrMappingEmitter.cpp
b/llvm/utils/TableGen/X86InstrMappingEmitter.cpp
index e8039db11d784..f967344135553 100644
--- a/llvm/utils/TableGen/X86InstrMappingEmitter.cpp
+++ b/llvm/utils/TableGen/X86InstrMappingEmitter.cpp
@@ -339,20 +339,27 @@ void X86InstrMappingEmitter::emitND2NonNDTable(
void X86InstrMappingEmitter::emitSSE2AVXTable(
ArrayRef<const CodeGenInstruction *> Insts, raw_ostream &OS) {
+
+ const std::map<StringRef, StringRef> ManualMap = {
+#define ENTRY_SSE2AVX(OLD, NEW) {#OLD, #NEW},
+#include "X86ManualInstrMapping.def"
+ };
+
std::vector<Entry> Table;
for (const CodeGenInstruction *Inst : Insts) {
const Record *Rec = Inst->TheDef;
StringRef Name = Rec->getName();
if (!isInteresting(Rec))
continue;
- auto *NewRec = Records.getDef(Name);
- if (!NewRec)
+ if (ManualMap.find(Name) != ManualMap.end()) {
+ auto *NewRec = Records.getDef(ManualMap.at(Rec->getName()));
+ assert(NewRec && "Instruction not found!");
+ auto &NewInst = Target.getInstruction(NewRec);
+ Table.push_back(std::pair(Inst, &NewInst));
continue;
+ }
std::string NewName = ("V" + Name).str();
- // Handle instructions BLENDVPD, BLENDVPS ,PBLENDVB
- if (Name.ends_with("rm0") || Name.ends_with("rr0"))
- NewName.back() = 'r';
auto *AVXRec = Records.getDef(NewName);
if (!AVXRec)
continue;
diff --git a/llvm/utils/TableGen/X86ManualInstrMapping.def
b/llvm/utils/TableGen/X86ManualInstrMapping.def
index 364f15607f73d..58f5449f3b27b 100644
--- a/llvm/utils/TableGen/X86ManualInstrMapping.def
+++ b/llvm/utils/TableGen/X86ManualInstrMapping.def
@@ -349,3 +349,14 @@ NOCOMP_ND(CFCMOV64rr_ND)
ENTRY_ND(MOVBE32rr, BSWAP32r)
ENTRY_ND(MOVBE64rr, BSWAP64r)
#undef ENTRY_ND
+
+#ifndef ENTRY_SSE2AVX
+#define ENTRY_SSE2AVX(OLD, NEW)
+#endif
+ENTRY_SSE2AVX(BLENDVPDrm0, VBLENDVPDrmr)
+ENTRY_SSE2AVX(BLENDVPDrr0, VBLENDVPDrrr)
+ENTRY_SSE2AVX(BLENDVPSrm0, VBLENDVPSrmr)
+ENTRY_SSE2AVX(BLENDVPSrr0, VBLENDVPSrrr)
+ENTRY_SSE2AVX(PBLENDVBrm0, VPBLENDVBrmr)
+ENTRY_SSE2AVX(PBLENDVBrr0, VPBLENDVBrrr)
+#undef ENTRY_SSE2AVX
>From 800ae6b925e0556fb94bc6c5784c2f3e7e3f5426 Mon Sep 17 00:00:00 2001
From: Chauhan Jaydeep Ashwinbhai <chauhan.jaydeep.ashwinb...@intel.com>
Date: Fri, 12 Jul 2024 16:18:26 +0800
Subject: [PATCH 14/14] Addressed review comments
---
clang/lib/Driver/ToolChains/Clang.cpp | 3 -
clang/test/Driver/{sse2avx.c => msse2avx.c} | 1 +
clang/test/Driver/sse2avx.s | 3 -
llvm/lib/MC/MCTargetOptionsCommandFlags.cpp | 3 +-
.../lib/Target/X86/AsmParser/X86AsmParser.cpp | 24 ++---
llvm/test/MC/AsmParser/sse2avx-att.s | 1 +
llvm/test/MC/AsmParser/sse2avx-intel.s | 88 -------------------
7 files changed, 16 insertions(+), 107 deletions(-)
rename clang/test/Driver/{sse2avx.c => msse2avx.c} (53%)
delete mode 100644 clang/test/Driver/sse2avx.s
delete mode 100644 llvm/test/MC/AsmParser/sse2avx-intel.s
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp
b/clang/lib/Driver/ToolChains/Clang.cpp
index 227e034ca5ea4..7689f9486c162 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -8369,9 +8369,6 @@ void ClangAs::AddX86TargetArgs(const ArgList &Args,
addX86AlignBranchArgs(getToolChain().getDriver(), Args, CmdArgs,
/*IsLTO=*/false);
- if (Args.hasArg(options::OPT_msse2avx))
- Args.AddLastArg(CmdArgs, options::OPT_msse2avx);
-
if (Arg *A = Args.getLastArg(options::OPT_masm_EQ)) {
StringRef Value = A->getValue();
if (Value == "intel" || Value == "att") {
diff --git a/clang/test/Driver/sse2avx.c b/clang/test/Driver/msse2avx.c
similarity index 53%
rename from clang/test/Driver/sse2avx.c
rename to clang/test/Driver/msse2avx.c
index da2aa53277fc9..42d1d481d9f28 100644
--- a/clang/test/Driver/sse2avx.c
+++ b/clang/test/Driver/msse2avx.c
@@ -1,3 +1,4 @@
// RUN: %clang -### -c -march=x86-64 -msse2avx %s 2>&1 | FileCheck %s
+// RUN: %clang -### -c -march=x86-64 -x assembler -msse2avx %s 2>&1 |
FileCheck %s
// CHECK: "-msse2avx"
diff --git a/clang/test/Driver/sse2avx.s b/clang/test/Driver/sse2avx.s
deleted file mode 100644
index 2277cb5798456..0000000000000
--- a/clang/test/Driver/sse2avx.s
+++ /dev/null
@@ -1,3 +0,0 @@
-// RUN: %clang -### -c -march=x86-64 -msse2avx %s 2>&1 | FileCheck %s
-
-// CHECK: "-msse2avx"
diff --git a/llvm/lib/MC/MCTargetOptionsCommandFlags.cpp
b/llvm/lib/MC/MCTargetOptionsCommandFlags.cpp
index 813cebbc07bde..813b1194b47cb 100644
--- a/llvm/lib/MC/MCTargetOptionsCommandFlags.cpp
+++ b/llvm/lib/MC/MCTargetOptionsCommandFlags.cpp
@@ -142,7 +142,8 @@
llvm::mc::RegisterMCTargetOptionsFlags::RegisterMCTargetOptionsFlags() {
MCBINDOPT(X86RelaxRelocations);
static cl::opt<bool> X86Sse2Avx(
- "x86-sse2avx", cl::desc("Convert SSE Instructions to AVX Instructions"));
+ "x86-sse2avx", cl::desc("Specify that the assembler should encode SSE "
+ "instructions with VEX prefix"));
MCBINDOPT(X86Sse2Avx);
static cl::opt<std::string> ABIName(
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index f24fb393a304f..9ecf5c0fdb27d 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -3749,26 +3749,26 @@ bool
X86AsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
return false;
}
-static void replaceSSE2AVXOpcode(MCInst &Inst) {
+static bool convertSSEToAVX(MCInst &Inst) {
ArrayRef<X86TableEntry> Table{X86SSE2AVXTable};
unsigned Opcode = Inst.getOpcode();
const auto I = llvm::lower_bound(Table, Opcode);
- if (I != Table.end() && I->OldOpc == Opcode)
- Inst.setOpcode(I->NewOpc);
+ if (I == Table.end() || I->OldOpc != Opcode)
+ return false;
+ Inst.setOpcode(I->NewOpc);
+ // AVX variant of BLENDVPD/BLENDVPS/PBLENDVB instructions has more
+ // operand compare to SSE variant, which is added below
if (X86::isBLENDVPD(Opcode) || X86::isBLENDVPS(Opcode) ||
- X86::isPBLENDVB(Opcode)) {
- unsigned RegNo = Inst.getOperand(2).getReg();
- Inst.addOperand(MCOperand::createReg(RegNo));
- }
+ X86::isPBLENDVB(Opcode))
+ Inst.addOperand(Inst.getOperand(2));
+
+ return true;
}
bool X86AsmParser::processInstruction(MCInst &Inst, const OperandVector &Ops) {
- // When "-msse2avx" option is enabled replaceSSE2AVXOpcode method will
- // replace SSE instruction with equivalent AVX instruction using mapping
given
- // in table GET_X86_SSE2AVX_TABLE
- if (MCOptions.X86Sse2Avx)
- replaceSSE2AVXOpcode(Inst);
+ if (MCOptions.X86Sse2Avx && convertSSEToAVX(Inst))
+ return true;
if (ForcedOpcodePrefix != OpcodePrefix_VEX3 &&
X86::optimizeInstFromVEX3ToVEX2(Inst, MII.get(Inst.getOpcode())))
diff --git a/llvm/test/MC/AsmParser/sse2avx-att.s
b/llvm/test/MC/AsmParser/sse2avx-att.s
index 363529fb7ef27..a452a5c611d3a 100644
--- a/llvm/test/MC/AsmParser/sse2avx-att.s
+++ b/llvm/test/MC/AsmParser/sse2avx-att.s
@@ -1,4 +1,5 @@
# RUN: llvm-mc -triple x86_64 -x86-sse2avx %s | FileCheck %s
+# RUN: llvm-mc -triple=x86_64 -output-asm-variant=1 %s | llvm-mc
-triple=x86_64 -x86-asm-syntax=intel -x86-sse2avx
.text
# CHECK: vmovsd -352(%rbp), %xmm0
movsd -352(%rbp), %xmm0 # xmm0 = mem[0],zero
diff --git a/llvm/test/MC/AsmParser/sse2avx-intel.s
b/llvm/test/MC/AsmParser/sse2avx-intel.s
deleted file mode 100644
index 9c8d03863693c..0000000000000
--- a/llvm/test/MC/AsmParser/sse2avx-intel.s
+++ /dev/null
@@ -1,88 +0,0 @@
-# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -x86-sse2avx %s |
FileCheck %s
- .text
-# CHECK: vmovsd -352(%rbp), %xmm0
- movsd xmm0, qword ptr [rbp - 352] # xmm0 = mem[0],zero
-# CHECK-NEXT: vunpcklpd %xmm1, %xmm0, %xmm0 # xmm0 = xmm0[0],xmm1[0]
- unpcklpd xmm0, xmm1 # xmm0 = xmm0[0],xmm1[0]
-# CHECK-NEXT: vmovapd %xmm0, -368(%rbp)
- movapd xmmword ptr [rbp - 368], xmm0
-# CHECK-NEXT: vmovapd -368(%rbp), %xmm0
- movapd xmm0, xmmword ptr [rbp - 368]
-# CHECK-NEXT: vmovapd %xmm0, -432(%rbp)
- movapd xmmword ptr [rbp - 432], xmm0
-# CHECK-NEXT: movabsq $4613937818241073152, %rax # imm =
0x4008000000000000
- movabs rax, 4613937818241073152
-# CHECK-NEXT: vunpcklpd %xmm1, %xmm0, %xmm0 # xmm0 = xmm0[0],xmm1[0]
- unpcklpd xmm0, xmm1 # xmm0 = xmm0[0],xmm1[0]
-# CHECK-NEXT: vaddpd %xmm1, %xmm0, %xmm0
- addpd xmm0, xmm1
-# CHECK-NEXT: vmovapd %xmm0, -464(%rbp)
- movapd xmmword ptr [rbp - 464], xmm0
-# CHECK-NEXT: vmovaps -304(%rbp), %xmm1
- movaps xmm1, xmmword ptr [rbp - 304]
-# CHECK-NEXT: vpandn %xmm1, %xmm0, %xmm0
- pandn xmm0, xmm1
-# CHECK-NEXT: vmovaps %xmm0, -480(%rbp)
- movaps xmmword ptr [rbp - 480], xmm0
-# CHECK-NEXT: vmovss -220(%rbp), %xmm1
- movss xmm1, dword ptr [rbp - 220] # xmm1 = mem[0],zero,zero,zero
-# CHECK-NEXT: vinsertps $16, %xmm1, %xmm0, %xmm0 # xmm0 =
xmm0[0],xmm1[0],xmm0[2,3]
- insertps xmm0, xmm1, 16 # xmm0 =
xmm0[0],xmm1[0],xmm0[2,3]
-# CHECK-NEXT: vmovaps %xmm0, -496(%rbp)
- movaps xmmword ptr [rbp - 496], xmm0
-# CHECK-NEXT: vmovss -252(%rbp), %xmm1
- movss xmm1, dword ptr [rbp - 252] # xmm1 = mem[0],zero,zero,zero
-# CHECK-NEXT: vmovaps %xmm1, -192(%rbp)
- movaps xmmword ptr [rbp - 192], xmm1
-# CHECK-NEXT: vdivss %xmm1, %xmm0, %xmm0
- divss xmm0, xmm1
-# CHECK-NEXT: vmovaps %xmm0, -192(%rbp)
- movaps xmmword ptr [rbp - 192], xmm0
-# CHECK-NEXT: vmovd -128(%rbp), %xmm0
- movd xmm0, dword ptr [rbp - 128] # xmm0 = mem[0],zero,zero,zero
-# CHECK-NEXT: vpinsrd $1, %edx, %xmm0, %xmm0
- pinsrd xmm0, edx, 1
-# CHECK-NEXT: vmovaps %xmm0, -144(%rbp)
- movaps xmmword ptr [rbp - 144], xmm0
-# CHECK-NEXT: vmovd -160(%rbp), %xmm0
- movd xmm0, dword ptr [rbp - 160] # xmm0 = mem[0],zero,zero,zero
-# CHECK-NEXT: vpblendw $170, %xmm1, %xmm0, %xmm0 # xmm0 =
xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7]
- pblendw xmm0, xmm1, 170 # xmm0 =
xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7]
-# CHECK-NEXT: vmovdqa %xmm0, -576(%rbp)
- movdqa xmmword ptr [rbp - 576], xmm0
-# CHECK-NEXT: vphsubw %xmm1, %xmm0, %xmm0
- phsubw xmm0, xmm1
-# CHECK-NEXT: vmovdqa %xmm0, -592(%rbp)
- movdqa xmmword ptr [rbp - 592], xmm0
-# CHECK-NEXT: vmovaps -496(%rbp), %xmm0
- movaps xmm0, xmmword ptr [rbp - 496]
-# CHECK-NEXT: vroundps $8, %xmm0, %xmm0
- roundps xmm0, xmm0, 8
-# CHECK-NEXT: vmovaps %xmm0, -608(%rbp)
- movaps xmmword ptr [rbp - 608], xmm0
-# CHECK-NEXT: vmovapd -432(%rbp), %xmm0
- movapd xmm0, xmmword ptr [rbp - 432]
-# CHECK-NEXT: vpxor %xmm1, %xmm0, %xmm0
- pxor xmm0, xmm1
-# CHECK-NEXT: vmovaps %xmm0, -640(%rbp)
- movaps xmmword ptr [rbp - 640], xmm0
-# CHECK-NEXT: vmovapd %xmm0, -32(%rbp)
- movapd xmmword ptr [rbp - 32], xmm0
-# CHECK-NEXT: vmovupd %xmm0, (%rax)
- movupd xmmword ptr [rax], xmm0
-# CHECK-NEXT: vmovsd -656(%rbp), %xmm0
- movsd xmm0, qword ptr [rbp - 656] # xmm0 = mem[0],zero
-# CHECK-NEXT: extrq $8, $16, %xmm0 # xmm0 =
xmm0[1,2],zero,zero,zero,zero,zero,zero,xmm0[u,u,u,u,u,u,u,u]
- extrq xmm0, 16, 8
-# CHECK-NEXT: insertq $8, $16, %xmm1, %xmm0 # xmm0 =
xmm0[0],xmm1[0,1],xmm0[3,4,5,6,7,u,u,u,u,u,u,u,u]
- insertq xmm0, xmm1, 16, 8
-# CHECK-NEXT: pshufw $1, %mm0, %mm2 # mm2 = mm0[1,0,0,0]
- pshufw mm2, mm0, 1
-# CHECK-NEXT: vpblendvb %xmm2, %xmm2, %xmm1, %xmm1
- pblendvb xmm1, xmm2, xmm0
-# CHECK-NEXT: vblendvps %xmm0, %xmm0, %xmm2, %xmm2
- blendvps xmm2, xmm0, xmm0
-# CHECK-NEXT: vblendvpd %xmm0, %xmm0, %xmm2, %xmm2
- blendvpd xmm2, xmm0, xmm0
-# CHECK-NEXT: vblendvpd %xmm0, %xmm0, %xmm2, %xmm2
- blendvpd xmm2, xmm0
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