================
@@ -3745,7 +3749,27 @@ bool X86AsmParser::ParseInstruction(ParseInstructionInfo
&Info, StringRef Name,
return false;
}
+static void replaceSSE2AVXOpcode(MCInst &Inst) {
+ ArrayRef<X86TableEntry> Table{X86SSE2AVXTable};
+ unsigned Opcode = Inst.getOpcode();
+ const auto I = llvm::lower_bound(Table, Opcode);
+ if (I != Table.end() && I->OldOpc == Opcode)
+ Inst.setOpcode(I->NewOpc);
+
+ if (X86::isBLENDVPD(Opcode) || X86::isBLENDVPS(Opcode) ||
+ X86::isPBLENDVB(Opcode)) {
+ unsigned RegNo = Inst.getOperand(2).getReg();
+ Inst.addOperand(MCOperand::createReg(RegNo));
+ }
+}
+
bool X86AsmParser::processInstruction(MCInst &Inst, const OperandVector &Ops) {
+ // When "-msse2avx" option is enabled replaceSSE2AVXOpcode method will
+ // replace SSE instruction with equivalent AVX instruction using mapping
given
+ // in table GET_X86_SSE2AVX_TABLE
----------------
MaskRay wrote:
Agree. `if (X86::isBLENDVPD(Opcode) || X86::isBLENDVPS(Opcode) || ..` needs a
comment.
https://github.com/llvm/llvm-project/pull/96860
_______________________________________________
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
