================
@@ -381,3 +381,20 @@ def XIANGSHAN_NANHU :
RISCVProcessorModel<"xiangshan-nanhu",
TuneZExtHFusion,
TuneZExtWFusion,
TuneShiftedZExtWFusion]>;
+
+def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60",
+ NoSchedModel,
+ !listconcat(RVA22S64Features,
+ [FeatureStdExtV,
+ FeatureStdExtSvnapot,
+ FeatureStdExtZbc,
+ FeatureStdExtZbkc,
+ FeatureStdExtZfh,
+ FeatureStdExtZicond,
----------------
preames wrote:
Looking at e.g. zicond, I don't see anything in the docs which claim support
for this extension. ruapu appears to work via running an instruction and
checking for faults - this could be a dangerous thing to rely on if the CPU
e.g. incorrectly implements some extension, or doesn't implement the reserved
opcodes the way the tool expects.
I suggest that we cut down this list to include *only* those things which are
specified. We can expand that list later based on changes to documentation
and/or communication with vendor.
https://github.com/llvm/llvm-project/pull/94564
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