github-actions[bot] wrote:
<!--LLVM CODE FORMAT COMMENT: {clang-format}-->
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
<details>
<summary>
You can test this locally with the following command:
</summary>
``````````bash
git-clang-format --diff 6a3982f8b7e37987659706cb3e6427c54c9bc7ce
d5e151568e1ebea81aabdcc42f753393095610e9 -- clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/Tooling/Inclusions/Stdlib/CSymbolMap.inc
clang/lib/Tooling/Inclusions/Stdlib/StdSymbolMap.inc
clang/test/CodeGen/builtins.c clang/test/CodeGen/math-libcalls.c
llvm/include/llvm/ADT/APFloat.h llvm/include/llvm/Analysis/IVDescriptors.h
llvm/include/llvm/Analysis/ValueTracking.h
llvm/include/llvm/CodeGen/BasicTTIImpl.h
llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
llvm/include/llvm/CodeGen/GlobalISel/Utils.h
llvm/include/llvm/CodeGen/ISDOpcodes.h
llvm/include/llvm/CodeGen/TargetLowering.h llvm/include/llvm/IR/IRBuilder.h
llvm/include/llvm/IR/IntrinsicInst.h llvm/lib/Analysis/ConstantFolding.cpp
llvm/lib/Analysis/IVDescriptors.cpp llvm/lib/Analysis/InstructionSimplify.cpp
llvm/lib/Analysis/ValueTracking.cpp llvm/lib/Analysis/VectorUtils.cpp
llvm/lib/CodeGen/ExpandVectorPredication.cpp
llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp
llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
llvm/lib/CodeGen/GlobalISel/Utils.cpp
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/lib/CodeGen/TargetLoweringBase.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/lib/Target/X86/X86TargetTransformInfo.cpp
llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
llvm/unittests/ADT/APFloatTest.cpp
llvm/unittests/Analysis/TargetLibraryInfoTest.cpp
llvm/unittests/IR/VPIntrinsicTest.cpp
``````````
</details>
<details>
<summary>
View the diff from clang-format here.
</summary>
``````````diff
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index f2a15dc9cf..76507c1357 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -2794,9 +2794,9 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl
GD, unsigned BuiltinID,
case Builtin::BI__builtin_fmaximum_numf16:
case Builtin::BI__builtin_fmaximum_numl:
case Builtin::BI__builtin_fmaximum_numf128:
- return RValue::get(emitBinaryMaybeConstrainedFPBuiltin(*this, E,
- Intrinsic::maximumnum,
-
Intrinsic::experimental_constrained_maximumnum));
+ return RValue::get(emitBinaryMaybeConstrainedFPBuiltin(
+ *this, E, Intrinsic::maximumnum,
+ Intrinsic::experimental_constrained_maximumnum));
case Builtin::BIfminimum_num:
case Builtin::BIfminimum_numf:
@@ -2806,9 +2806,9 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl
GD, unsigned BuiltinID,
case Builtin::BI__builtin_fminimum_numf16:
case Builtin::BI__builtin_fminimum_numl:
case Builtin::BI__builtin_fminimum_numf128:
- return RValue::get(emitBinaryMaybeConstrainedFPBuiltin(*this, E,
- Intrinsic::minnum,
-
Intrinsic::experimental_constrained_minimumnum));
+ return RValue::get(emitBinaryMaybeConstrainedFPBuiltin(
+ *this, E, Intrinsic::minnum,
+ Intrinsic::experimental_constrained_minimumnum));
// fmod() is a special-case. It maps to the frem instruction rather than an
// LLVM intrinsic.
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 2339b0d792..6de4a1d8fd 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -808,18 +808,38 @@ AArch64TargetLowering::AArch64TargetLowering(const
TargetMachine &TM,
setOperationAction(ISD::FP_ROUND, MVT::v4bf16, Custom);
// AArch64 has implementations of a lot of rounding-like FP operations.
- for (auto Op :
- {ISD::FFLOOR, ISD::FNEARBYINT, ISD::FCEIL,
- ISD::FRINT, ISD::FTRUNC, ISD::FROUND,
- ISD::FROUNDEVEN, ISD::FMINNUM, ISD::FMAXNUM,
- ISD::FMINNUM_IEEE, ISD::FMAXNUM_IEEE,
- ISD::FMINIMUM, ISD::FMAXIMUM, ISD::LROUND,
- ISD::LLROUND, ISD::LRINT, ISD::LLRINT,
- ISD::STRICT_FFLOOR, ISD::STRICT_FCEIL, ISD::STRICT_FNEARBYINT,
- ISD::STRICT_FRINT, ISD::STRICT_FTRUNC, ISD::STRICT_FROUNDEVEN,
- ISD::STRICT_FROUND, ISD::STRICT_FMINNUM, ISD::STRICT_FMAXNUM,
- ISD::STRICT_FMINIMUM, ISD::STRICT_FMAXIMUM, ISD::STRICT_LROUND,
- ISD::STRICT_LLROUND, ISD::STRICT_LRINT, ISD::STRICT_LLRINT}) {
+ for (auto Op : {ISD::FFLOOR,
+ ISD::FNEARBYINT,
+ ISD::FCEIL,
+ ISD::FRINT,
+ ISD::FTRUNC,
+ ISD::FROUND,
+ ISD::FROUNDEVEN,
+ ISD::FMINNUM,
+ ISD::FMAXNUM,
+ ISD::FMINNUM_IEEE,
+ ISD::FMAXNUM_IEEE,
+ ISD::FMINIMUM,
+ ISD::FMAXIMUM,
+ ISD::LROUND,
+ ISD::LLROUND,
+ ISD::LRINT,
+ ISD::LLRINT,
+ ISD::STRICT_FFLOOR,
+ ISD::STRICT_FCEIL,
+ ISD::STRICT_FNEARBYINT,
+ ISD::STRICT_FRINT,
+ ISD::STRICT_FTRUNC,
+ ISD::STRICT_FROUNDEVEN,
+ ISD::STRICT_FROUND,
+ ISD::STRICT_FMINNUM,
+ ISD::STRICT_FMAXNUM,
+ ISD::STRICT_FMINIMUM,
+ ISD::STRICT_FMAXIMUM,
+ ISD::STRICT_LROUND,
+ ISD::STRICT_LLROUND,
+ ISD::STRICT_LRINT,
+ ISD::STRICT_LLRINT}) {
for (MVT Ty : {MVT::f32, MVT::f64})
setOperationAction(Op, Ty, Legal);
if (Subtarget->hasFullFP16())
@@ -1129,25 +1149,56 @@ AArch64TargetLowering::AArch64TargetLowering(const
TargetMachine &TM,
if (Subtarget->isNeonAvailable()) {
// FIXME: v1f64 shouldn't be legal if we can avoid it, because it leads to
// silliness like this:
- for (auto Op :
- {ISD::SELECT, ISD::SELECT_CC,
- ISD::BR_CC, ISD::FADD, ISD::FSUB,
- ISD::FMUL, ISD::FDIV, ISD::FMA,
- ISD::FNEG, ISD::FABS, ISD::FCEIL,
- ISD::FSQRT, ISD::FFLOOR, ISD::FNEARBYINT,
- ISD::FSIN, ISD::FCOS, ISD::FPOW,
- ISD::FLOG, ISD::FLOG2, ISD::FLOG10,
- ISD::FEXP, ISD::FEXP2, ISD::FEXP10,
- ISD::FRINT, ISD::FROUND, ISD::FROUNDEVEN,
- ISD::FTRUNC, ISD::FMINNUM, ISD::FMAXNUM,
- ISD::FMINNUM_IEEE, ISD::FMAXNUM_IEEE,
- ISD::FMINIMUM, ISD::FMAXIMUM, ISD::STRICT_FADD,
- ISD::STRICT_FSUB, ISD::STRICT_FMUL, ISD::STRICT_FDIV,
- ISD::STRICT_FMA, ISD::STRICT_FCEIL, ISD::STRICT_FFLOOR,
- ISD::STRICT_FSQRT, ISD::STRICT_FRINT, ISD::STRICT_FNEARBYINT,
- ISD::STRICT_FROUND, ISD::STRICT_FTRUNC, ISD::STRICT_FROUNDEVEN,
- ISD::STRICT_FMINNUM, ISD::STRICT_FMAXNUM, ISD::STRICT_FMINIMUM,
- ISD::STRICT_FMAXIMUM})
+ for (auto Op : {ISD::SELECT,
+ ISD::SELECT_CC,
+ ISD::BR_CC,
+ ISD::FADD,
+ ISD::FSUB,
+ ISD::FMUL,
+ ISD::FDIV,
+ ISD::FMA,
+ ISD::FNEG,
+ ISD::FABS,
+ ISD::FCEIL,
+ ISD::FSQRT,
+ ISD::FFLOOR,
+ ISD::FNEARBYINT,
+ ISD::FSIN,
+ ISD::FCOS,
+ ISD::FPOW,
+ ISD::FLOG,
+ ISD::FLOG2,
+ ISD::FLOG10,
+ ISD::FEXP,
+ ISD::FEXP2,
+ ISD::FEXP10,
+ ISD::FRINT,
+ ISD::FROUND,
+ ISD::FROUNDEVEN,
+ ISD::FTRUNC,
+ ISD::FMINNUM,
+ ISD::FMAXNUM,
+ ISD::FMINNUM_IEEE,
+ ISD::FMAXNUM_IEEE,
+ ISD::FMINIMUM,
+ ISD::FMAXIMUM,
+ ISD::STRICT_FADD,
+ ISD::STRICT_FSUB,
+ ISD::STRICT_FMUL,
+ ISD::STRICT_FDIV,
+ ISD::STRICT_FMA,
+ ISD::STRICT_FCEIL,
+ ISD::STRICT_FFLOOR,
+ ISD::STRICT_FSQRT,
+ ISD::STRICT_FRINT,
+ ISD::STRICT_FNEARBYINT,
+ ISD::STRICT_FROUND,
+ ISD::STRICT_FTRUNC,
+ ISD::STRICT_FROUNDEVEN,
+ ISD::STRICT_FMINNUM,
+ ISD::STRICT_FMAXNUM,
+ ISD::STRICT_FMINIMUM,
+ ISD::STRICT_FMAXIMUM})
setOperationAction(Op, MVT::v1f64, Expand);
for (auto Op :
@@ -1827,11 +1878,10 @@ void AArch64TargetLowering::addTypeForNEON(MVT VT) {
(VT.getVectorElementType() != MVT::f16 || Subtarget->hasFullFP16()))
for (unsigned Opcode :
{ISD::FMINIMUM, ISD::FMAXIMUM, ISD::FMINNUM, ISD::FMAXNUM,
- ISD::FMINNUM_IEEE, ISD::FMAXNUM_IEEE,
- ISD::STRICT_FMINIMUM, ISD::STRICT_FMAXIMUM, ISD::STRICT_FMINNUM,
- ISD::STRICT_FMAXNUM, ISD::STRICT_FADD, ISD::STRICT_FSUB,
- ISD::STRICT_FMUL, ISD::STRICT_FDIV, ISD::STRICT_FMA,
- ISD::STRICT_FSQRT})
+ ISD::FMINNUM_IEEE, ISD::FMAXNUM_IEEE, ISD::STRICT_FMINIMUM,
+ ISD::STRICT_FMAXIMUM, ISD::STRICT_FMINNUM, ISD::STRICT_FMAXNUM,
+ ISD::STRICT_FADD, ISD::STRICT_FSUB, ISD::STRICT_FMUL,
+ ISD::STRICT_FDIV, ISD::STRICT_FMA, ISD::STRICT_FSQRT})
setOperationAction(Opcode, VT, Legal);
// Strict fp extend and trunc are legal
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index 3810d71fd4..c8e97e1043 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -1642,29 +1642,77 @@ HexagonTargetLowering::HexagonTargetLowering(const
TargetMachine &TM,
// Set the action for vector operations to "expand", then override it with
// either "custom" or "legal" for specific cases.
static const unsigned VectExpOps[] = {
- // Integer arithmetic:
- ISD::ADD, ISD::SUB, ISD::MUL, ISD::SDIV, ISD::UDIV,
- ISD::SREM, ISD::UREM, ISD::SDIVREM, ISD::UDIVREM, ISD::SADDO,
- ISD::UADDO, ISD::SSUBO, ISD::USUBO, ISD::SMUL_LOHI, ISD::UMUL_LOHI,
- // Logical/bit:
- ISD::AND, ISD::OR, ISD::XOR, ISD::ROTL, ISD::ROTR,
- ISD::CTPOP, ISD::CTLZ, ISD::CTTZ, ISD::BSWAP, ISD::BITREVERSE,
- // Floating point arithmetic/math functions:
- ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FMA, ISD::FDIV,
- ISD::FREM, ISD::FNEG, ISD::FABS, ISD::FSQRT, ISD::FSIN,
- ISD::FCOS, ISD::FPOW, ISD::FLOG, ISD::FLOG2,
- ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FCEIL, ISD::FTRUNC,
- ISD::FRINT, ISD::FNEARBYINT, ISD::FROUND, ISD::FFLOOR,
- ISD::FMINNUM, ISD::FMAXNUM, ISD::FSINCOS, ISD::FLDEXP,
- ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM,
- // Misc:
- ISD::BR_CC, ISD::SELECT_CC, ISD::ConstantPool,
- // Vector:
- ISD::BUILD_VECTOR, ISD::SCALAR_TO_VECTOR,
- ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT,
- ISD::EXTRACT_SUBVECTOR, ISD::INSERT_SUBVECTOR,
- ISD::CONCAT_VECTORS, ISD::VECTOR_SHUFFLE,
- ISD::SPLAT_VECTOR,
+ // Integer arithmetic:
+ ISD::ADD,
+ ISD::SUB,
+ ISD::MUL,
+ ISD::SDIV,
+ ISD::UDIV,
+ ISD::SREM,
+ ISD::UREM,
+ ISD::SDIVREM,
+ ISD::UDIVREM,
+ ISD::SADDO,
+ ISD::UADDO,
+ ISD::SSUBO,
+ ISD::USUBO,
+ ISD::SMUL_LOHI,
+ ISD::UMUL_LOHI,
+ // Logical/bit:
+ ISD::AND,
+ ISD::OR,
+ ISD::XOR,
+ ISD::ROTL,
+ ISD::ROTR,
+ ISD::CTPOP,
+ ISD::CTLZ,
+ ISD::CTTZ,
+ ISD::BSWAP,
+ ISD::BITREVERSE,
+ // Floating point arithmetic/math functions:
+ ISD::FADD,
+ ISD::FSUB,
+ ISD::FMUL,
+ ISD::FMA,
+ ISD::FDIV,
+ ISD::FREM,
+ ISD::FNEG,
+ ISD::FABS,
+ ISD::FSQRT,
+ ISD::FSIN,
+ ISD::FCOS,
+ ISD::FPOW,
+ ISD::FLOG,
+ ISD::FLOG2,
+ ISD::FLOG10,
+ ISD::FEXP,
+ ISD::FEXP2,
+ ISD::FCEIL,
+ ISD::FTRUNC,
+ ISD::FRINT,
+ ISD::FNEARBYINT,
+ ISD::FROUND,
+ ISD::FFLOOR,
+ ISD::FMINNUM,
+ ISD::FMAXNUM,
+ ISD::FSINCOS,
+ ISD::FLDEXP,
+ ISD::FMINIMUMNUM,
+ ISD::FMAXIMUMNUM,
+ // Misc:
+ ISD::BR_CC,
+ ISD::SELECT_CC,
+ ISD::ConstantPool,
+ // Vector:
+ ISD::BUILD_VECTOR,
+ ISD::SCALAR_TO_VECTOR,
+ ISD::EXTRACT_VECTOR_ELT,
+ ISD::INSERT_VECTOR_ELT,
+ ISD::EXTRACT_SUBVECTOR,
+ ISD::INSERT_SUBVECTOR,
+ ISD::CONCAT_VECTORS,
+ ISD::VECTOR_SHUFFLE,
+ ISD::SPLAT_VECTOR,
};
for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 03c290aa8a..5323035afe 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -702,22 +702,46 @@ RISCVTargetLowering::RISCVTargetLowering(const
TargetMachine &TM,
ISD::VP_SADDSAT, ISD::VP_UADDSAT, ISD::VP_SSUBSAT,
ISD::VP_USUBSAT, ISD::VP_CTTZ_ELTS,
ISD::VP_CTTZ_ELTS_ZERO_UNDEF};
- static const unsigned FloatingPointVPOps[] = {
- ISD::VP_FADD, ISD::VP_FSUB, ISD::VP_FMUL,
- ISD::VP_FDIV, ISD::VP_FNEG, ISD::VP_FABS,
- ISD::VP_FMA, ISD::VP_REDUCE_FADD, ISD::VP_REDUCE_SEQ_FADD,
- ISD::VP_REDUCE_FMIN, ISD::VP_REDUCE_FMAX, ISD::VP_MERGE,
- ISD::VP_SELECT, ISD::VP_SINT_TO_FP, ISD::VP_UINT_TO_FP,
- ISD::VP_SETCC, ISD::VP_FP_ROUND, ISD::VP_FP_EXTEND,
- ISD::VP_SQRT, ISD::VP_FMINNUM, ISD::VP_FMAXNUM,
- ISD::VP_FCEIL, ISD::VP_FFLOOR, ISD::VP_FROUND,
- ISD::VP_FROUNDEVEN, ISD::VP_FCOPYSIGN, ISD::VP_FROUNDTOZERO,
- ISD::VP_FRINT, ISD::VP_FNEARBYINT, ISD::VP_IS_FPCLASS,
- ISD::VP_FMINIMUM, ISD::VP_FMAXIMUM, ISD::VP_LRINT,
- ISD::VP_FMINIMUMNUM, ISD::VP_FMAXIMUMNUM,
- ISD::VP_LLRINT, ISD::EXPERIMENTAL_VP_REVERSE,
- ISD::EXPERIMENTAL_VP_SPLICE, ISD::VP_REDUCE_FMINIMUM,
- ISD::VP_REDUCE_FMAXIMUM};
+ static const unsigned FloatingPointVPOps[] = {ISD::VP_FADD,
+ ISD::VP_FSUB,
+ ISD::VP_FMUL,
+ ISD::VP_FDIV,
+ ISD::VP_FNEG,
+ ISD::VP_FABS,
+ ISD::VP_FMA,
+ ISD::VP_REDUCE_FADD,
+ ISD::VP_REDUCE_SEQ_FADD,
+ ISD::VP_REDUCE_FMIN,
+ ISD::VP_REDUCE_FMAX,
+ ISD::VP_MERGE,
+ ISD::VP_SELECT,
+ ISD::VP_SINT_TO_FP,
+ ISD::VP_UINT_TO_FP,
+ ISD::VP_SETCC,
+ ISD::VP_FP_ROUND,
+ ISD::VP_FP_EXTEND,
+ ISD::VP_SQRT,
+ ISD::VP_FMINNUM,
+ ISD::VP_FMAXNUM,
+ ISD::VP_FCEIL,
+ ISD::VP_FFLOOR,
+ ISD::VP_FROUND,
+ ISD::VP_FROUNDEVEN,
+ ISD::VP_FCOPYSIGN,
+ ISD::VP_FROUNDTOZERO,
+ ISD::VP_FRINT,
+ ISD::VP_FNEARBYINT,
+ ISD::VP_IS_FPCLASS,
+ ISD::VP_FMINIMUM,
+ ISD::VP_FMAXIMUM,
+ ISD::VP_LRINT,
+ ISD::VP_FMINIMUMNUM,
+ ISD::VP_FMAXIMUMNUM,
+ ISD::VP_LLRINT,
+ ISD::EXPERIMENTAL_VP_REVERSE,
+ ISD::EXPERIMENTAL_VP_SPLICE,
+ ISD::VP_REDUCE_FMINIMUM,
+ ISD::VP_REDUCE_FMAXIMUM};
static const unsigned IntegerVecReduceOps[] = {
ISD::VECREDUCE_ADD, ISD::VECREDUCE_AND, ISD::VECREDUCE_OR,
@@ -945,27 +969,45 @@ RISCVTargetLowering::RISCVTargetLowering(const
TargetMachine &TM,
// TODO: support more ops.
static const unsigned ZvfhminPromoteOps[] = {
- ISD::FMINNUM, ISD::FMAXNUM, ISD::FADD, ISD::FSUB,
- ISD::FMUL, ISD::FMA, ISD::FDIV, ISD::FSQRT,
- ISD::FABS, ISD::FNEG, ISD::FCOPYSIGN, ISD::FCEIL,
- ISD::FFLOOR, ISD::FROUND, ISD::FROUNDEVEN, ISD::FRINT,
- ISD::FNEARBYINT, ISD::IS_FPCLASS, ISD::SETCC, ISD::FMAXIMUM,
- ISD::FMINIMUM, ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM,
- ISD::STRICT_FADD, ISD::STRICT_FSUB, ISD::STRICT_FMUL,
- ISD::STRICT_FDIV, ISD::STRICT_FSQRT, ISD::STRICT_FMA};
+ ISD::FMINNUM, ISD::FMAXNUM, ISD::FADD, ISD::FSUB,
+ ISD::FMUL, ISD::FMA, ISD::FDIV, ISD::FSQRT,
+ ISD::FABS, ISD::FNEG, ISD::FCOPYSIGN, ISD::FCEIL,
+ ISD::FFLOOR, ISD::FROUND, ISD::FROUNDEVEN, ISD::FRINT,
+ ISD::FNEARBYINT, ISD::IS_FPCLASS, ISD::SETCC, ISD::FMAXIMUM,
+ ISD::FMINIMUM, ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM, ISD::STRICT_FADD,
+ ISD::STRICT_FSUB, ISD::STRICT_FMUL, ISD::STRICT_FDIV,
ISD::STRICT_FSQRT,
+ ISD::STRICT_FMA};
// TODO: support more vp ops.
- static const unsigned ZvfhminPromoteVPOps[] = {
- ISD::VP_FADD, ISD::VP_FSUB, ISD::VP_FMUL,
- ISD::VP_FDIV, ISD::VP_FNEG, ISD::VP_FABS,
- ISD::VP_FMA, ISD::VP_REDUCE_FADD, ISD::VP_REDUCE_SEQ_FADD,
- ISD::VP_REDUCE_FMIN, ISD::VP_REDUCE_FMAX, ISD::VP_SQRT,
- ISD::VP_FMINNUM, ISD::VP_FMAXNUM, ISD::VP_FCEIL,
- ISD::VP_FFLOOR, ISD::VP_FROUND, ISD::VP_FROUNDEVEN,
- ISD::VP_FCOPYSIGN, ISD::VP_FROUNDTOZERO, ISD::VP_FRINT,
- ISD::VP_FNEARBYINT, ISD::VP_SETCC, ISD::VP_FMINIMUM,
- ISD::VP_FMAXIMUM, ISD::VP_REDUCE_FMINIMUM, ISD::VP_REDUCE_FMAXIMUM,
- ISD::VP_FMINIMUMNUM, ISD::VP_FMAXIMUMNUM};
+ static const unsigned ZvfhminPromoteVPOps[] = {ISD::VP_FADD,
+ ISD::VP_FSUB,
+ ISD::VP_FMUL,
+ ISD::VP_FDIV,
+ ISD::VP_FNEG,
+ ISD::VP_FABS,
+ ISD::VP_FMA,
+ ISD::VP_REDUCE_FADD,
+ ISD::VP_REDUCE_SEQ_FADD,
+ ISD::VP_REDUCE_FMIN,
+ ISD::VP_REDUCE_FMAX,
+ ISD::VP_SQRT,
+ ISD::VP_FMINNUM,
+ ISD::VP_FMAXNUM,
+ ISD::VP_FCEIL,
+ ISD::VP_FFLOOR,
+ ISD::VP_FROUND,
+ ISD::VP_FROUNDEVEN,
+ ISD::VP_FCOPYSIGN,
+ ISD::VP_FROUNDTOZERO,
+ ISD::VP_FRINT,
+ ISD::VP_FNEARBYINT,
+ ISD::VP_SETCC,
+ ISD::VP_FMINIMUM,
+ ISD::VP_FMAXIMUM,
+ ISD::VP_REDUCE_FMINIMUM,
+ ISD::VP_REDUCE_FMAXIMUM,
+ ISD::VP_FMINIMUMNUM,
+ ISD::VP_FMAXIMUMNUM};
// Sets common operation actions on RVV floating-point vector types.
const auto SetCommonVFPActions = [&](MVT VT) {
diff --git a/llvm/unittests/IR/VPIntrinsicTest.cpp
b/llvm/unittests/IR/VPIntrinsicTest.cpp
index 94bee42e9f..e6390678f7 100644
--- a/llvm/unittests/IR/VPIntrinsicTest.cpp
+++ b/llvm/unittests/IR/VPIntrinsicTest.cpp
@@ -27,9 +27,9 @@ namespace {
static const char *ReductionIntOpcodes[] = {
"add", "mul", "and", "or", "xor", "smin", "smax", "umin", "umax"};
-static const char *ReductionFPOpcodes[] = {"fadd", "fmul", "fmin",
- "fmax", "fminimum", "fmaximum",
- "fminimumnum", "fmaximumnum"};
+static const char *ReductionFPOpcodes[] = {
+ "fadd", "fmul", "fmin", "fmax",
+ "fminimum", "fmaximum", "fminimumnum", "fmaximumnum"};
class VPIntrinsicTest : public testing::Test {
protected:
@@ -50,10 +50,9 @@ protected:
Str << " declare <8 x i32> @llvm.vp." << BinaryIntOpcode
<< ".v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32) ";
- const char *BinaryFPOpcodes[] = {"fadd", "fsub", "fmul", "fdiv",
- "frem", "minnum", "maxnum", "minimum",
- "maximum", "minimumnum", "maximumnum",
- "copysign"};
+ const char *BinaryFPOpcodes[] = {
+ "fadd", "fsub", "fmul", "fdiv", "frem", "minnum",
+ "maxnum", "minimum", "maximum", "minimumnum", "maximumnum",
"copysign"};
for (const char *BinaryFPOpcode : BinaryFPOpcodes)
Str << " declare <8 x float> @llvm.vp." << BinaryFPOpcode
<< ".v8f32(<8 x float>, <8 x float>, <8 x i1>, i32) ";
``````````
</details>
https://github.com/llvm/llvm-project/pull/93841
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