================
@@ -98,9 +96,34 @@ BitVector SparcRegisterInfo::getReservedRegs(const
MachineFunction &MF) const {
for (unsigned n = 0; n < 31; n++)
Reserved.set(SP::ASR1 + n);
+ for (size_t i = 0; i < SP::IntRegsRegClass.getNumRegs() / 4; ++i) {
+ // Mark both single register and register pairs.
+ if (MF.getSubtarget<SparcSubtarget>().isGRegisterReserved(i)) {
+ Reserved.set(SP::G0 + i);
+ Reserved.set(SP::G0_G1 + i / 2);
+ }
+ if (MF.getSubtarget<SparcSubtarget>().isORegisterReserved(i)) {
+ Reserved.set(SP::O0 + i);
+ Reserved.set(SP::O0_O1 + i / 2);
+ }
+ if (MF.getSubtarget<SparcSubtarget>().isLRegisterReserved(i)) {
+ Reserved.set(SP::L0 + i);
+ Reserved.set(SP::L0_L1 + i / 2);
+ }
+ if (MF.getSubtarget<SparcSubtarget>().isIRegisterReserved(i)) {
+ Reserved.set(SP::I0 + i);
+ Reserved.set(SP::I0_I1 + i / 2);
+ }
+ }
+
return Reserved;
----------------
koachan wrote:
checkAllSuperRegsMarked returns a bool though, no? We want a BitVector here...
https://github.com/llvm/llvm-project/pull/74927
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