================
@@ -80,6 +86,11 @@ class SparcSubtarget : public SparcGenSubtargetInfo {
return is64Bit() ? 2047 : 0;
}
+ bool isGRegisterReserved(size_t i) const { return ReserveGRegister[i]; }
+ bool isORegisterReserved(size_t i) const { return ReserveORegister[i]; }
+ bool isLRegisterReserved(size_t i) const { return ReserveLRegister[i]; }
+ bool isIRegisterReserved(size_t i) const { return ReserveIRegister[i]; }
----------------
s-barannikov wrote:
This could be a single interface accepting a physical register instead of an
index.
https://github.com/llvm/llvm-project/pull/74927
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