craig.topper added inline comments.
================ Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:1972 +// Control Flow Integerity +include "RISCVInstrInfoZicfiss.td" ---------------- Put this with the other RISCVInstrInfoZi* files under "Integer" ================ Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td:92 +let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1 in +def C_SSPUSHX1 : RVC_SSInst<0b00001, "c.sspush", "x1">; + ---------------- Can we merge the X1 and X5 instructions? Looks like the register is encoded? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D152793/new/ https://reviews.llvm.org/D152793 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
