craig.topper added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:233
+def uimm10 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isUInt<10>(Imm);}]> {
+ let ParserMatchClass = UImmAsmOperand<10>;
----------------
Is this used?
================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td:35
+class RV_SSPop<bits<5> _rd, bits<5> _rs1, string opcodestr, string argstr> :
+ RVInstI<0b100, OPC_SYSTEM, (outs GPR:$rd), (ins GPR:$rs1), opcodestr,
argstr> {
+ let rd = _rd;
----------------
Why are there ins and outs here that aren't encoded?
================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZicfiss.td:56
+let Predicates = [HasStdExtZicfiss] in {
+def SSLoadX1: RV_SSPop<0b00001, 0b00000, "ssload", "x1">;
+def SSLoadX5: RV_SSPop<0b00101, 0b00000, "ssload", "x5">;
----------------
Need to be able to parse with `ra` instead of x1 and `t0` instead of x5.
I think you might need a new Operand type so the parse can parse it as a
register.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D152793/new/
https://reviews.llvm.org/D152793
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