pengfei accepted this revision.
pengfei added a comment.
This revision is now accepted and ready to land.
I have some concerns for RULE 3, especially `core_aes_pclmulqdq -> westmere`
and `atom_sse4_2_movbe -> silvermont`.
Sometimes, we have minor feature differences in the same generation targets. I
guess that's why we use `arch_feature` naming like core_2_duo_ssse3. Merging
them into the same generation or the next generation might corrup the intention
here. But I'm not expert in CPUDispatch, and I don't see any existing tests for
them, so I won't block the patch since it's an improvement in general.
Please wait a few days for other reviewers' opinions.
================
Comment at: clang/test/CodeGen/attr-cpuspecific.c:56
// WINDOWS: %[[FEAT_INIT:.+]] = load i32, ptr getelementptr inbounds ({ i32,
i32, i32, [1 x i32] }, ptr @__cpu_model, i32 0, i32 3, i32 0), align 4
-// WINDOWS: %[[FEAT_JOIN:.+]] = and i32 %[[FEAT_INIT]], 1023
-// WINDOWS: %[[FEAT_CHECK:.+]] = icmp eq i32 %[[FEAT_JOIN]], 1023
+// WINDOWS: %[[FEAT_JOIN:.+]] = and i32 %[[FEAT_INIT]], 525311
+// WINDOWS: %[[FEAT_CHECK:.+]] = icmp eq i32 %[[FEAT_JOIN]], 525311
----------------
FreddyYe wrote:
> This value change is because the feature list of knl described in
> X86TargetParser.def before missed feature "bmi2" and "aes".
The comment is for TwoVersions?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D151696/new/
https://reviews.llvm.org/D151696
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