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Reserve X18 even when -fsanitize=shadow-call-stack is not enabled.
Based on: https://reviews.llvm.org/D143355
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D145999
Files:
clang/test/Driver/riscv-fixed-x-register.c
llvm/lib/TargetParser/RISCVTargetParser.cpp
llvm/test/CodeGen/RISCV/reserved-regs.ll
Index: llvm/test/CodeGen/RISCV/reserved-regs.ll
===================================================================
--- llvm/test/CodeGen/RISCV/reserved-regs.ll
+++ llvm/test/CodeGen/RISCV/reserved-regs.ll
@@ -58,6 +58,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+reserve-x31 -verify-machineinstrs < %s |
FileCheck %s -check-prefix=X31
; RUN: llc -mtriple=riscv64-fuchsia -verify-machineinstrs < %s | FileCheck %s
-check-prefix=X18
+; RUN: llc -mtriple=riscv64-linux-android -verify-machineinstrs < %s |
FileCheck %s -check-prefix=X18
; This program is free to use all registers, but needs a stack pointer for
; spill values, so do not test for reserving the stack pointer.
Index: llvm/lib/TargetParser/RISCVTargetParser.cpp
===================================================================
--- llvm/lib/TargetParser/RISCVTargetParser.cpp
+++ llvm/lib/TargetParser/RISCVTargetParser.cpp
@@ -103,7 +103,7 @@
bool isX18ReservedByDefault(const Triple &TT) {
// X18 is reserved for the ShadowCallStack ABI (even when not enabled).
- return TT.isOSFuchsia();
+ return TT.isOSFuchsia() || TT.isAndroid();
}
} // namespace RISCV
Index: clang/test/Driver/riscv-fixed-x-register.c
===================================================================
--- clang/test/Driver/riscv-fixed-x-register.c
+++ clang/test/Driver/riscv-fixed-x-register.c
@@ -339,3 +339,8 @@
// RUN: --check-prefix=CHECK-FIXED-X30 \
// RUN: --check-prefix=CHECK-FIXED-X31 \
// RUN: < %t %s
+
+// Check that x18 is reserved on Android by default
+// RUN: %clang --target=riscv64-linux-android -### %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-ANDROID-FIXED-X18 < %t %s
+// CHECK-ANDROID-FIXED-X18: "-target-feature" "+reserve-x18"
Index: llvm/test/CodeGen/RISCV/reserved-regs.ll
===================================================================
--- llvm/test/CodeGen/RISCV/reserved-regs.ll
+++ llvm/test/CodeGen/RISCV/reserved-regs.ll
@@ -58,6 +58,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+reserve-x31 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X31
; RUN: llc -mtriple=riscv64-fuchsia -verify-machineinstrs < %s | FileCheck %s -check-prefix=X18
+; RUN: llc -mtriple=riscv64-linux-android -verify-machineinstrs < %s | FileCheck %s -check-prefix=X18
; This program is free to use all registers, but needs a stack pointer for
; spill values, so do not test for reserving the stack pointer.
Index: llvm/lib/TargetParser/RISCVTargetParser.cpp
===================================================================
--- llvm/lib/TargetParser/RISCVTargetParser.cpp
+++ llvm/lib/TargetParser/RISCVTargetParser.cpp
@@ -103,7 +103,7 @@
bool isX18ReservedByDefault(const Triple &TT) {
// X18 is reserved for the ShadowCallStack ABI (even when not enabled).
- return TT.isOSFuchsia();
+ return TT.isOSFuchsia() || TT.isAndroid();
}
} // namespace RISCV
Index: clang/test/Driver/riscv-fixed-x-register.c
===================================================================
--- clang/test/Driver/riscv-fixed-x-register.c
+++ clang/test/Driver/riscv-fixed-x-register.c
@@ -339,3 +339,8 @@
// RUN: --check-prefix=CHECK-FIXED-X30 \
// RUN: --check-prefix=CHECK-FIXED-X31 \
// RUN: < %t %s
+
+// Check that x18 is reserved on Android by default
+// RUN: %clang --target=riscv64-linux-android -### %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-ANDROID-FIXED-X18 < %t %s
+// CHECK-ANDROID-FIXED-X18: "-target-feature" "+reserve-x18"
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