arsenm added inline comments.
================ Comment at: llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td:49 + CCIfType<[bf16], CCBitConvertToType<i16>>, + CCIfType<[v2bf16], CCBitConvertToType<i32>>, CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[ ---------------- Without being added to a register class, all the tablegen changes should not do anything Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D139398/new/ https://reviews.llvm.org/D139398 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
