palmer-dabbelt updated this revision to Diff 438515.
palmer-dabbelt added a comment.
Herald added a subscriber: jdoerfert.
- Fix a whitespace issue
- Fix the name of RISCVInstrInfoZawrs.td
- Call the #define __riscv_zawrs instead of __riscv_wrs, to match the others
- Add tests in clang/test/Driver/riscv-arch.c,
clang/test/Preprocessor/riscv-target-features.c,
llvm/test/CodeGen/RISCV/attributes.ll
The clang tests aren't running for me, presumably because clang isn't building
locally. Also hoping to rely on CI for that one, but I'm not entirely sure.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D128235/new/
https://reviews.llvm.org/D128235
Files:
clang/lib/Basic/Targets/RISCV.cpp
clang/test/Driver/riscv-arch.c
clang/test/Preprocessor/riscv-target-features.c
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/Target/RISCV/RISCVInstrInfoZawrs.td
llvm/lib/Target/RISCV/RISCVSubtarget.h
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/MC/RISCV/zawrs-invalid.s
llvm/test/MC/RISCV/zawrs-valid.s
Index: llvm/test/MC/RISCV/zawrs-valid.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/zawrs-valid.s
@@ -0,0 +1,16 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zawrs \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zawrs \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zawrs < %s \
+# RUN: | llvm-objdump --mattr=+zawrs -d -r - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zawrs < %s \
+# RUN: | llvm-objdump --mattr=+zawrs -d -r - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+
+# CHECK-S-OBJ: wrs
+wrs
+
+# CHECK-S-OBJ: wrs t0
+wrs t0
Index: llvm/test/MC/RISCV/zawrs-invalid.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/zawrs-invalid.s
@@ -0,0 +1,8 @@
+# RUN: not llvm-mc -triple riscv64 -mattr=+a < %s 2>&1 | FileCheck %s
+
+# WRS doesn't take immediates
+wrs 1 # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
+
+# WRS only takes at most a single register
+wrs t0, 1 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+wrs t0, t0 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
Index: llvm/test/CodeGen/RISCV/attributes.ll
===================================================================
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -36,6 +36,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+zkn,+zkr,+zkt %s -o - | FileCheck --check-prefix=RV32COMBINEINTOZK %s
; RUN: llc -mtriple=riscv32 -mattr=+zbkb,+zbkc,+zbkx,+zkne,+zknd,+zknh %s -o - | FileCheck --check-prefix=RV32COMBINEINTOZKN %s
; RUN: llc -mtriple=riscv32 -mattr=+zbkb,+zbkc,+zbkx,+zksed,+zksh %s -o - | FileCheck --check-prefix=RV32COMBINEINTOZKS %s
+; RUN: llc -mtriple=riscv32 -mattr=+zawrs %s -o - | FileCheck --check-prefix=RV32ZAWRS %s
; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefix=RV64A %s
; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefix=RV64F %s
@@ -72,6 +73,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+zkn,+zkr,+zkt %s -o - | FileCheck --check-prefix=RV64COMBINEINTOZK %s
; RUN: llc -mtriple=riscv64 -mattr=+zbkb,+zbkc,+zbkx,+zkne,+zknd,+zknh %s -o - | FileCheck --check-prefix=RV64COMBINEINTOZKN %s
; RUN: llc -mtriple=riscv64 -mattr=+zbkb,+zbkc,+zbkx,+zksed,+zksh %s -o - | FileCheck --check-prefix=RV64COMBINEINTOZKS %s
+; RUN: llc -mtriple=riscv64 -mattr=+zawrs %s -o - | FileCheck --check-prefix=RV64ZAWRS %s
; RV32M: .attribute 5, "rv32i2p0_m2p0"
; RV32A: .attribute 5, "rv32i2p0_a2p0"
@@ -109,6 +111,7 @@
; RV32COMBINEINTOZK: .attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0"
; RV32COMBINEINTOZKN: .attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0"
; RV32COMBINEINTOZKS: .attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0"
+; RV32ZAWRS: .attribute 5, "rv32i2p0_zawrs1p0"
; RV64M: .attribute 5, "rv64i2p0_m2p0"
; RV64A: .attribute 5, "rv64i2p0_a2p0"
@@ -146,6 +149,7 @@
; RV64COMBINEINTOZK: .attribute 5, "rv64i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0"
; RV64COMBINEINTOZKN: .attribute 5, "rv64i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0"
; RV64COMBINEINTOZKS: .attribute 5, "rv64i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0"
+; RV64ZAWRS: .attribute 5, "rv64i2p0_zawrs1p0"
define i32 @addi(i32 %a) {
%1 = add i32 %a, 1
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===================================================================
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -86,6 +86,7 @@
bool HasStdExtZks = false;
bool HasStdExtZkt = false;
bool HasStdExtZk = false;
+ bool HasStdExtZawrs = false;
bool HasRV64 = false;
bool IsRV32E = false;
bool EnableLinkerRelax = false;
@@ -177,6 +178,7 @@
bool hasStdExtZksed() const { return HasStdExtZksed; }
bool hasStdExtZksh() const { return HasStdExtZksh; }
bool hasStdExtZkr() const { return HasStdExtZkr; }
+ bool hasStdExtZawrs() const { return HasStdExtZawrs; }
bool is64Bit() const { return HasRV64; }
bool isRV32E() const { return IsRV32E; }
bool enableLinkerRelax() const { return EnableLinkerRelax; }
Index: llvm/lib/Target/RISCV/RISCVInstrInfoZawrs.td
===================================================================
--- /dev/null
+++ llvm/lib/Target/RISCV/RISCVInstrInfoZawrs.td
@@ -0,0 +1,21 @@
+//===-- RISCVInstrInfoZawrs.td - RISC-V 'Zawrs' instructions -------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the RISC-V instructions from the standard 'Zawrs', Wait
+// Reservation Set, extension.
+//
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtZawrs], hasSideEffects = 1, mayStore = 0, mayLoad = 0 in {
+ def WRS : RVInstI<0b000, OPC_SYSTEM, (outs), (ins GPR:$rs1), "wrs", "$rs1">, Sched<[]> {
+ let rd = 0;
+ let imm12 = 0x010;
+ }
+}
+
+def : InstAlias<"wrs", (WRS X0)>;
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1648,3 +1648,4 @@
include "RISCVInstrInfoZk.td"
include "RISCVInstrInfoV.td"
include "RISCVInstrInfoZfh.td"
+include "RISCVInstrInfoZawrs.td"
Index: llvm/lib/Target/RISCV/RISCV.td
===================================================================
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -400,6 +400,14 @@
"'Zvfh' (Vector Half-Precision Floating-Point)",
[FeatureStdExtZve32f]>;
+def FeatureStdExtZawrs
+ : SubtargetFeature<"zawrs", "HasStdExtZawrs", "true",
+ "'Zawrs' (Wait Reservation Set)">;
+def HasStdExtZawrs
+ : Predicate<"Subtarget->hasStdExtZawrs">,
+ AssemblerPredicate<(any_of FeatureStdExtZawrs),
+ "'Zawrs' (Wait Reservation Set) ">;
+
def Feature64Bit
: SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;
def IsRV64 : Predicate<"Subtarget->is64Bit()">,
Index: llvm/lib/Support/RISCVISAInfo.cpp
===================================================================
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -50,6 +50,8 @@
{"zihintpause", RISCVExtensionVersion{2, 0}},
+ {"zawrs", RISCVExtensionVersion{1, 0}},
+
{"zfhmin", RISCVExtensionVersion{1, 0}},
{"zfh", RISCVExtensionVersion{1, 0}},
Index: clang/test/Preprocessor/riscv-target-features.c
===================================================================
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -42,6 +42,7 @@
// CHECK-NOT: __riscv_zkr
// CHECK-NOT: __riscv_zkt
// CHECK-NOT: __riscv_zk
+// CHECK-NOT: __riscv_zawrs
// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s
@@ -433,3 +434,11 @@
// RUN: -march=rv64i_zbkb_zbkc_zbkx_zksed_zksh -x c -E -dM %s -o - \
// RUN: | FileCheck --check-prefix=CHECK-COMBINE-INTO-ZKS %s
// CHECK-COMBINE-INTO-ZKS: __riscv_zks 1
+
+// RUN: %clang -target riscv32-unknown-linux-gnu \
+// RUN: -march=rv32i_zawrs -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZAWRS %s
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64i_zawrs -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZAWRS %s
+// CHECK-COMBINE-INTO-ZKS: __riscv_zawrs 1
Index: clang/test/Driver/riscv-arch.c
===================================================================
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -579,3 +579,11 @@
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZHINX-BADVERS %s
// RV32-ZHINX-BADVERS: error: invalid arch name 'rv32izhinx0p1'
// RV32-ZHINX-BADVERS: unsupported version number 0.1 for extension 'zhinx'
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32izawrs1p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZAWRS-GOOD %s
+// RV32-ZHINX-GOOD: "-target-feature" "+zawrs"
+
+// RUN: %clang --target=riscv64-unknown-elf -march=rv64izawrs1p0 -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV64-ZAWRS-GOOD %s
+// RV64-ZHINX-GOOD: "-target-feature" "+zawrs"
Index: clang/lib/Basic/Targets/RISCV.cpp
===================================================================
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -190,6 +190,9 @@
if (ISAInfo->hasExtension("zve32x"))
Builder.defineMacro("__riscv_vector");
+
+ if (ISAInfo->hasExtension("zawrs"))
+ Builder.defineMacro("__riscv_zawrs");
}
const Builtin::Info RISCVTargetInfo::BuiltinInfo[] = {
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