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This extension contains a single instruction, wrs, which waits for the
current reservation set to be modified by a remote agent.
Signed-off-by: Palmer Dabbelt <pal...@rivosinc.com>
---
This is still some sort of very early draft and I'm not sure what the
rules are in LLVM land for merging that sort of code. It's a fast track
extension so it should be done soon, but it's been drifting around a bit
as part of that process so this might not be sane right now. I'm really
just doing this to check the box on LLVM support, which is just
assembler support due to the nature of the WRS instruction.
I also haven't gotten clang-format working yet, but I'm hoping something
in the CI will help with that.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D128235
Files:
clang/lib/Basic/Targets/RISCV.cpp
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/Target/RISCV/RISCVInstrInfoZawrs.td
llvm/lib/Target/RISCV/RISCVSubtarget.h
llvm/test/MC/RISCV/zawrs-invalid.s
llvm/test/MC/RISCV/zawrs-valid.s
Index: llvm/test/MC/RISCV/zawrs-valid.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/zawrs-valid.s
@@ -0,0 +1,16 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zawrs \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zawrs \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zawrs < %s \
+# RUN: | llvm-objdump --mattr=+zawrs -d -r - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zawrs < %s \
+# RUN: | llvm-objdump --mattr=+zawrs -d -r - \
+# RUN: | FileCheck -check-prefixes=CHECK-S-OBJ %s
+
+# CHECK-S-OBJ: wrs
+wrs
+
+# CHECK-S-OBJ: wrs t0
+wrs t0
Index: llvm/test/MC/RISCV/zawrs-invalid.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/zawrs-invalid.s
@@ -0,0 +1,8 @@
+# RUN: not llvm-mc -triple riscv64 -mattr=+a < %s 2>&1 | FileCheck %s
+
+# WRS doesn't take immediates
+wrs 1 # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
+
+# WRS only takes at most a single register
+wrs t0, 1 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+wrs t0, t0 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===================================================================
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -86,6 +86,7 @@
bool HasStdExtZks = false;
bool HasStdExtZkt = false;
bool HasStdExtZk = false;
+ bool HasStdExtZawrs = false;
bool HasRV64 = false;
bool IsRV32E = false;
bool EnableLinkerRelax = false;
@@ -177,6 +178,7 @@
bool hasStdExtZksed() const { return HasStdExtZksed; }
bool hasStdExtZksh() const { return HasStdExtZksh; }
bool hasStdExtZkr() const { return HasStdExtZkr; }
+ bool hasStdExtZawrs() const { return HasStdExtZawrs; }
bool is64Bit() const { return HasRV64; }
bool isRV32E() const { return IsRV32E; }
bool enableLinkerRelax() const { return EnableLinkerRelax; }
Index: llvm/lib/Target/RISCV/RISCVInstrInfoZawrs.td
===================================================================
--- /dev/null
+++ llvm/lib/Target/RISCV/RISCVInstrInfoZawrs.td
@@ -0,0 +1,21 @@
+//===-- RISCVInstrInfoM.td - RISC-V 'M' instructions -------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the RISC-V instructions from the standard 'Zawrs', Wait
+// Reservation Set, extension.
+//
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtZawrs], hasSideEffects = 1, mayStore = 0, mayLoad = 0 in {
+ def WRS : RVInstI<0b000, OPC_SYSTEM, (outs), (ins GPR:$rs1), "wrs", "$rs1">, Sched<[]> {
+ let rd = 0;
+ let imm12 = 0x010;
+ }
+}
+
+def : InstAlias<"wrs", (WRS X0)>;
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1648,3 +1648,4 @@
include "RISCVInstrInfoZk.td"
include "RISCVInstrInfoV.td"
include "RISCVInstrInfoZfh.td"
+include "RISCVInstrInfoZawrs.td"
Index: llvm/lib/Target/RISCV/RISCV.td
===================================================================
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -400,6 +400,14 @@
"'Zvfh' (Vector Half-Precision Floating-Point)",
[FeatureStdExtZve32f]>;
+def FeatureStdExtZawrs
+ : SubtargetFeature<"zawrs", "HasStdExtZawrs", "true",
+ "'Zawrs' (Wait Reservation Set)">;
+def HasStdExtZawrs
+ : Predicate<"Subtarget->hasStdExtZawrs">,
+ AssemblerPredicate<(any_of FeatureStdExtZawrs),
+ "'Zawrs' (Wait Reservation Set) ">;
+
def Feature64Bit
: SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;
def IsRV64 : Predicate<"Subtarget->is64Bit()">,
Index: llvm/lib/Support/RISCVISAInfo.cpp
===================================================================
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -50,6 +50,8 @@
{"zihintpause", RISCVExtensionVersion{2, 0}},
+ {"zawrs", RISCVExtensionVersion{1, 0}},
+
{"zfhmin", RISCVExtensionVersion{1, 0}},
{"zfh", RISCVExtensionVersion{1, 0}},
Index: clang/lib/Basic/Targets/RISCV.cpp
===================================================================
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -190,6 +190,9 @@
if (ISAInfo->hasExtension("zve32x"))
Builder.defineMacro("__riscv_vector");
+
+ if (ISAInfo->hasExtension("zawrs"))
+ Builder.defineMacro("__riscv_wrs");
}
const Builtin::Info RISCVTargetInfo::BuiltinInfo[] = {
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