khchen updated this revision to Diff 406842.
khchen added a comment.
rebase on D119250 <https://reviews.llvm.org/D119250> to make changes clear.
Thanks for kito's suggestion!
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D118333/new/
https://reviews.llvm.org/D118333
Files:
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll
llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
llvm/test/CodeGen/RISCV/double-calling-conv.ll
llvm/test/CodeGen/RISCV/double-imm.ll
llvm/test/CodeGen/RISCV/double-mem.ll
llvm/test/CodeGen/RISCV/double-previous-failure.ll
llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
llvm/test/CodeGen/RISCV/fastcc-float.ll
llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll
llvm/test/CodeGen/RISCV/fpclamptosat.ll
llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll
llvm/test/CodeGen/RISCV/frm-dependency.ll
llvm/test/CodeGen/RISCV/inline-asm-clobbers.ll
llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll
llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
llvm/test/CodeGen/RISCV/mattr-invalid-combination.ll
llvm/test/CodeGen/RISCV/rv64d-double-convert-strict.ll
llvm/test/CodeGen/RISCV/rv64d-double-convert.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll
llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir
llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
llvm/test/CodeGen/RISCV/rvv/vmfeq-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
llvm/test/CodeGen/RISCV/select-const.ll
llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
llvm/test/CodeGen/RISCV/spill-fpr-scalar.ll
llvm/test/MC/RISCV/mattr-invalid-combination.s
Index: llvm/test/MC/RISCV/mattr-invalid-combination.s
===================================================================
--- llvm/test/MC/RISCV/mattr-invalid-combination.s
+++ llvm/test/MC/RISCV/mattr-invalid-combination.s
@@ -1,4 +1,4 @@
# RUN: not --crash llvm-mc -triple riscv64 -mattr=+e < %s 2>&1 \
# RUN: | FileCheck %s -check-prefix=RV64E
-# RV64E: LLVM ERROR: RV32E can't be enabled for an RV64 target
+# RV64E: LLVM ERROR: standard user-level extension 'e' requires 'rv32'
Index: llvm/test/CodeGen/RISCV/spill-fpr-scalar.ll
===================================================================
--- llvm/test/CodeGen/RISCV/spill-fpr-scalar.ll
+++ llvm/test/CodeGen/RISCV/spill-fpr-scalar.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh \
+; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh -target-abi=lp64 \
; RUN: -verify-machineinstrs < %s \
; RUN: | FileCheck %s
Index: llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
===================================================================
--- llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
+++ llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
@@ -1,11 +1,11 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I
-; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zbt -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zbt -target-abi=ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32IBT
-; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi=lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64I
-; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zbt -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zbt -target-abi=lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64IBT
; Selects of wide values are split into two selects, which can easily cause
Index: llvm/test/CodeGen/RISCV/select-const.ll
===================================================================
--- llvm/test/CodeGen/RISCV/select-const.ll
+++ llvm/test/CodeGen/RISCV/select-const.ll
@@ -1,19 +1,19 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -target-abi=ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
-; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi=ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IF %s
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -target-abi=ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IBT %s
-; RUN: llc -mtriple=riscv32 -mattr=+f,+experimental-zbt -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+f,+experimental-zbt -target-abi=ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IFBT %s
-; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -target-abi=lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s
-; RUN: llc -mtriple=riscv64 -mattr=+f,+d -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+f,+d -target-abi=lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IFD %s
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt -target-abi=lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IBT %s
-; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+experimental-zbt -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+experimental-zbt -target-abi=lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IFDBT %s
;; This tests how good we are at materialising constants using `select`. The aim
Index: llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
+++ llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+m,+f,+d,+a,+c,+v \
+; RUN: llc -mtriple=riscv64 -mattr=+m,+f,+d,+a,+c,+v -target-abi=lp64 \
; RUN: -verify-machineinstrs -O2 < %s | FileCheck %s
declare i64 @llvm.riscv.vsetvli(i64, i64, i64)
Index: llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
+++ llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+m,+f,+d,+a,+c,+v \
+; RUN: llc -mtriple=riscv64 -mattr=+m,+f,+d,+a,+c,+v -target-abi=lp64 \
; RUN: -verify-machineinstrs -O2 < %s | FileCheck %s
; The following tests check whether inserting VSETVLI avoids inserting
Index: llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll
+++ llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh -verify-machineinstrs \
+; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh -target-abi=lp64 -verify-machineinstrs \
; RUN: < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16(
<vscale x 1 x half>,
Index: llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll
+++ llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zfh -verify-machineinstrs \
+; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zfh -target-abi=ilp32 -verify-machineinstrs \
; RUN: < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16(
<vscale x 1 x half>,
Index: llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll
+++ llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh -verify-machineinstrs \
+; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh -target-abi=lp64 -verify-machineinstrs \
; RUN: < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16(
<vscale x 1 x half>,
Index: llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll
+++ llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zfh -verify-machineinstrs \
+; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zfh -target-abi=ilp32 -verify-machineinstrs \
; RUN: < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16(
<vscale x 1 x half>,
Index: llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll
+++ llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh -verify-machineinstrs \
+; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh -target-abi=lp64 -verify-machineinstrs \
; RUN: < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16(
<vscale x 1 x half>,
Index: llvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll
+++ llvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zfh -verify-machineinstrs \
+; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zfh -target-abi=ilp32 -verify-machineinstrs \
; RUN: < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16(
<vscale x 1 x half>,
Index: llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll
+++ llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh -verify-machineinstrs \
+; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh -target-abi=lp64 -verify-machineinstrs \
; RUN: < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16(
<vscale x 1 x half>,
Index: llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll
+++ llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zfh -verify-machineinstrs \
+; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zfh -target-abi=ilp32 -verify-machineinstrs \
; RUN: < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16(
<vscale x 1 x half>,
Index: llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll
+++ llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh -verify-machineinstrs \
+; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh -target-abi=lp64 -verify-machineinstrs \
; RUN: < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16(
<vscale x 1 x half>,
Index: llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll
+++ llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zfh -verify-machineinstrs \
+; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zfh -target-abi=ilp32 -verify-machineinstrs \
; RUN: < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16(
<vscale x 1 x half>,
Index: llvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll
+++ llvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh -verify-machineinstrs \
+; RUN: llc -mtriple=riscv64 -mattr=+v,+d,+zfh -target-abi=lp64 -verify-machineinstrs \
; RUN: < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16(
<vscale x 1 x half>,
Index: llvm/test/CodeGen/RISCV/rvv/vmfeq-rv32.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/vmfeq-rv32.ll
+++ llvm/test/CodeGen/RISCV/rvv/vmfeq-rv32.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zfh -verify-machineinstrs \
+; RUN: llc -mtriple=riscv32 -mattr=+v,+d,+zfh -target-abi=ilp32 -verify-machineinstrs \
; RUN: < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16(
<vscale x 1 x half>,
Index: llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
+++ llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v,+f \
+; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v,+f -target-abi=lp64 \
; RUN: -riscv-v-vector-bits-min=128 | FileCheck %s
define void @sink_splat_mul(i32* nocapture %a, i32 signext %x) {
Index: llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir
+++ llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-# RUN: llc -mtriple riscv64 -mattr=+m,+v -start-before=prologepilog -o - \
+# RUN: llc -mtriple riscv64 -mattr=+m,+v -target-abi=lp64 -start-before=prologepilog -o - \
# RUN: -verify-machineinstrs %s | FileCheck %s
--- |
target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll
+++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+v -verify-machineinstrs -riscv-v-vector-bits-min=128 < %s | FileCheck %s --check-prefixes=CHECK,RV32-FP
-; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+v -verify-machineinstrs -riscv-v-vector-bits-min=128 < %s | FileCheck %s --check-prefixes=CHECK,RV64-FP
+; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+v -target-abi=ilp32 -verify-machineinstrs -riscv-v-vector-bits-min=128 < %s | FileCheck %s --check-prefixes=CHECK,RV32-FP
+; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+v -target-abi=lp64 -verify-machineinstrs -riscv-v-vector-bits-min=128 < %s | FileCheck %s --check-prefixes=CHECK,RV64-FP
define i16 @bitcast_v1f16_i16(<1 x half> %a) {
; CHECK-LABEL: bitcast_v1f16_i16:
Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir
+++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-# RUN: llc -mtriple riscv64 -mattr=+v -start-before=prologepilog -o - \
+# NOTE: Assertions gave been autogenerated by utils/update_llc_test_checks.py
+# RUN: llc -mtriple riscv64 -mattr=+v -target-abi=lp64 -start-before=prologepilog -o - \
# RUN: -verify-machineinstrs %s | FileCheck %s
--- |
target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
Index: llvm/test/CodeGen/RISCV/rv64d-double-convert.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rv64d-double-convert.ll
+++ llvm/test/CodeGen/RISCV/rv64d-double-convert.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi=lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64ID
; This file exhaustively checks double<->i32 conversions. In general,
Index: llvm/test/CodeGen/RISCV/rv64d-double-convert-strict.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rv64d-double-convert-strict.ll
+++ llvm/test/CodeGen/RISCV/rv64d-double-convert-strict.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi=lp64 -verify-machineinstrs < %s \
; RUN: -disable-strictnode-mutation | FileCheck %s -check-prefix=RV64ID
; This file exhaustively checks double<->i32 conversions. In general,
Index: llvm/test/CodeGen/RISCV/mattr-invalid-combination.ll
===================================================================
--- llvm/test/CodeGen/RISCV/mattr-invalid-combination.ll
+++ llvm/test/CodeGen/RISCV/mattr-invalid-combination.ll
@@ -1,4 +1,5 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: not --crash llc -mtriple=riscv64 -mattr=+e < %s 2>&1 \
; RUN: | FileCheck -check-prefix=RV64E %s
-; RV64E: LLVM ERROR: RV32E can't be enabled for an RV64 target
+; RV64E: LLVM ERROR: standard user-level extension 'e' requires 'rv32'
Index: llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
===================================================================
--- llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
+++ llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
@@ -1,11 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
+; NOTE: Assertions gave been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi=ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32F %s
-; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64F %s
-; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32F %s
-; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi=lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64F %s
@gf = external global float
Index: llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll
===================================================================
--- llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll
+++ llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32F %s
-; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi=lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64F %s
@gd = external global double
Index: llvm/test/CodeGen/RISCV/inline-asm-clobbers.ll
===================================================================
--- llvm/test/CodeGen/RISCV/inline-asm-clobbers.ll
+++ llvm/test/CodeGen/RISCV/inline-asm-clobbers.ll
@@ -1,14 +1,14 @@
-; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -target-abi=ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
-; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -target-abi=lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s
-; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi=ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
-; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s
-; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
-; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi=lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s
; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IF %s
Index: llvm/test/CodeGen/RISCV/frm-dependency.ll
===================================================================
--- llvm/test/CodeGen/RISCV/frm-dependency.ll
+++ llvm/test/CodeGen/RISCV/frm-dependency.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+f,+d -stop-after=finalize-isel < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+f,+d -target-abi=ilp32 -stop-after=finalize-isel < %s \
; RUN: | FileCheck -check-prefixes=RV32IF %s
-; RUN: llc -mtriple=riscv64 -mattr=+f,+d -stop-after=finalize-isel < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+f,+d -target-abi=lp64 -stop-after=finalize-isel < %s \
; RUN: | FileCheck -check-prefixes=RV64IF %s
; Make sure an implicit FRM dependency is added to instructions with dynamic
Index: llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll
===================================================================
--- llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll
+++ llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+v -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+v -target-abi=lp64 -verify-machineinstrs < %s | FileCheck %s
; i32 saturate
Index: llvm/test/CodeGen/RISCV/fpclamptosat.ll
===================================================================
--- llvm/test/CodeGen/RISCV/fpclamptosat.ll
+++ llvm/test/CodeGen/RISCV/fpclamptosat.ll
@@ -1,11 +1,11 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi=ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV32,RV32IF %s
-; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64,RV64IF %s
-; RUN: llc -mtriple=riscv32 -mattr=+f,+d -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+f,+d -target-abi=ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV32,RV32IFD %s
-; RUN: llc -mtriple=riscv64 -mattr=+f,+d -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+f,+d -target-abi=lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefixes=RV64,RV64IFD %s
; i32 saturate
Index: llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll
===================================================================
--- llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll
+++ llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll
@@ -1,11 +1,11 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi=ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32F %s
-; RUN: llc -mtriple=riscv32 -mattr=+f,+d -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+f,+d -target-abi=ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32FD %s
-; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64F %s
-; RUN: llc -mtriple=riscv64 -mattr=+f,+d -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+f,+d -target-abi=lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64FD %s
; These functions perform extra work to ensure that `%a3` starts in a
Index: llvm/test/CodeGen/RISCV/fastcc-float.ll
===================================================================
--- llvm/test/CodeGen/RISCV/fastcc-float.ll
+++ llvm/test/CodeGen/RISCV/fastcc-float.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+f,+d -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+f,+d -target-abi=ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s
define fastcc float @callee(<32 x float> %A) nounwind {
Index: llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
===================================================================
--- llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
+++ llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IFD %s
-; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi=lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IFD %s
define double @func(double %d, i32 %n) nounwind {
Index: llvm/test/CodeGen/RISCV/double-previous-failure.ll
===================================================================
--- llvm/test/CodeGen/RISCV/double-previous-failure.ll
+++ llvm/test/CodeGen/RISCV/double-previous-failure.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IFD %s
define double @test(double %a) nounwind {
Index: llvm/test/CodeGen/RISCV/double-mem.ll
===================================================================
--- llvm/test/CodeGen/RISCV/double-mem.ll
+++ llvm/test/CodeGen/RISCV/double-mem.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IFD %s
-; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi=lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IFD %s
define dso_local double @fld(double *%a) nounwind {
Index: llvm/test/CodeGen/RISCV/double-imm.ll
===================================================================
--- llvm/test/CodeGen/RISCV/double-imm.ll
+++ llvm/test/CodeGen/RISCV/double-imm.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IFD %s
-; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi=lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IFD %s
define double @double_imm() nounwind {
Index: llvm/test/CodeGen/RISCV/double-calling-conv.ll
===================================================================
--- llvm/test/CodeGen/RISCV/double-calling-conv.ll
+++ llvm/test/CodeGen/RISCV/double-calling-conv.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IFD %s
; Basic correctness checks for calling convention lowering for RV32D. This can
Index: llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
===================================================================
--- llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
+++ llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
@@ -1,11 +1,11 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -target-abi=ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
-; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -target-abi=ilp32 -mattr=+d -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IFD %s
-; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -target-abi=lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s
-; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -target-abi=lp64 -mattr=+d -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IFD %s
;
; This file tests cases where simple floating point operations can be
Index: llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll
===================================================================
--- llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll
+++ llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=ILP32
-; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi=lp64 -verify-machineinstrs< %s \
; RUN: | FileCheck %s -check-prefix=LP64
; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=ILP32D
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
===================================================================
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
@@ -62,15 +62,11 @@
if (TargetABI != ABI_Unknown)
return TargetABI;
- // For now, default to the ilp32/ilp32e/lp64 ABI if no explicit ABI is given
- // or an invalid/unrecognised string is given. In the future, it might be
- // worth changing this to default to ilp32f/lp64f and ilp32d/lp64d when
- // hardware support for floating point is present.
- if (IsRV32E)
- return ABI_ILP32E;
- if (IsRV64)
- return ABI_LP64;
- return ABI_ILP32;
+ // If no explicit ABI is given, try to compute the default ABI.
+ auto ISAInfo = RISCVFeatures::parseFeatureBits(IsRV64, FeatureBits);
+ if (!ISAInfo)
+ report_fatal_error(ISAInfo.takeError());
+ return getTargetABI((*ISAInfo)->computeDefaultABI());
}
ABI getTargetABI(StringRef ABIName) {
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