[PATCH] D93298: [RISCV] add the part of MC layer support of Zfinx extension

[Craig Topper via Phabricator via cfe-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoF.td:124
 class FPFMA_rrr_frm<RISCVOpcode opcode, bits<2> funct2, string opcodestr,
-                    RegisterClass rty>
+                    RegisterOperand rty>
     : RVInstR4Frm<funct2, opcode, (outs rty:$rd),
----------------
Can we use `DAGOperand` instead of RegisterOperand? I think that should allow 
you to avoid adding GPROp, FPR32Op, FPR64Op, and FPR16Op. You can just use the 
RegisterClasses. Both RegisterClass and RegisterOperand inherit from DAGOperand.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93298/new/

https://reviews.llvm.org/D93298

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