achieveartificialintelligence updated this revision to Diff 397191.
achieveartificialintelligence added a comment.
Address @craig.topper 's comments.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D93298/new/
https://reviews.llvm.org/D93298
Files:
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/Target/RISCV/RISCVInstrInfoD.td
llvm/lib/Target/RISCV/RISCVInstrInfoF.td
llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
llvm/lib/Target/RISCV/RISCVRegisterInfo.td
llvm/lib/Target/RISCV/RISCVSubtarget.h
llvm/test/MC/RISCV/attribute-arch.s
llvm/test/MC/RISCV/rv32i-invalid.s
Index: llvm/test/MC/RISCV/rv32i-invalid.s
===================================================================
--- llvm/test/MC/RISCV/rv32i-invalid.s
+++ llvm/test/MC/RISCV/rv32i-invalid.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -triple riscv32 < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv32 %s 2>&1 | FileCheck %s
# Out of range immediates
## fencearg
@@ -173,6 +173,9 @@
amomaxu.w s5, s4, (s3) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'A' (Atomic Instructions)
fadd.s ft0, ft1, ft2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point)
fadd.h ft0, ft1, ft2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point)
+fadd.s a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfinx' (Float in Integer)
+fadd.d a0, a2, a4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zdinx' (Double in Integer)
+fadd.h a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zhinx' (Half Float in Integer)
# Using floating point registers when integer registers are expected
addi a2, ft0, 24 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
Index: llvm/test/MC/RISCV/attribute-arch.s
===================================================================
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -74,5 +74,17 @@
.attribute arch, "rv32ifzfh0p1"
# CHECK: attribute 5, "rv32i2p0_f2p0_zfh0p1_zfhmin0p1"
+.attribute arch, "rv32izfinx1p0"
+# CHECK: attribute 5, "rv32i2p0_zfinx1p0"
+
+.attribute arch, "rv32izdinx1p0"
+# CHECK: attribute 5, "rv32i2p0_zdinx1p0"
+
+.attribute arch, "rv32izhinxmin1p0"
+# CHECK: attribute 5, "rv32i2p0_zhinxmin1p0"
+
+.attribute arch, "rv32izhinx1p0"
+# CHECK: attribute 5, "rv32i2p0_zhinx1p0"
+
.attribute arch, "rv32iv0p10zvlsseg0p10"
# CHECK: attribute 5, "rv32i2p0_v0p10_zvlsseg0p10"
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===================================================================
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -53,6 +53,10 @@
bool HasStdExtZvlsseg = false;
bool HasStdExtZfhmin = false;
bool HasStdExtZfh = false;
+ bool HasStdExtZfinx = false;
+ bool HasStdExtZdinx = false;
+ bool HasStdExtZhinxmin = false;
+ bool HasStdExtZhinx = false;
bool HasRV64 = false;
bool IsRV32E = false;
bool EnableLinkerRelax = false;
@@ -119,6 +123,10 @@
bool hasStdExtZvlsseg() const { return HasStdExtZvlsseg; }
bool hasStdExtZfhmin() const { return HasStdExtZfhmin; }
bool hasStdExtZfh() const { return HasStdExtZfh; }
+ bool hasStdExtZfinx() const { return HasStdExtZfinx; }
+ bool hasStdExtZdinx() const { return HasStdExtZdinx; }
+ bool hasStdExtZhinxmin() const { return HasStdExtZhinxmin; }
+ bool hasStdExtZhinx() const { return HasStdExtZhinx; }
bool is64Bit() const { return HasRV64; }
bool isRV32E() const { return IsRV32E; }
bool enableLinkerRelax() const { return EnableLinkerRelax; }
Index: llvm/lib/Target/RISCV/RISCVRegisterInfo.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -66,6 +66,7 @@
def sub_vrm1_6 : ComposedSubRegIndex<sub_vrm2_3, sub_vrm1_0>;
def sub_vrm1_7 : ComposedSubRegIndex<sub_vrm2_3, sub_vrm1_1>;
+def sub_32_hi : SubRegIndex<32, 32>;
} // Namespace = "RISCV"
// Integer registers
@@ -557,6 +558,63 @@
let Size = 64;
}
+let RegAltNameIndices = [ABIRegAltName] in {
+ foreach Index = [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22,
+ 24, 26, 28, 30] in {
+ defvar Reg = !cast<Register>("X"#Index);
+ def X#Index#_PD : RISCVRegWithSubRegs<Index, Reg.AsmName,
+ [!cast<Register>("X"#Index),
+ !cast<Register>("X"#!add(Index, 1))],
+ Reg.AltNames> {
+ let SubRegIndices = [sub_32, sub_32_hi];
+ }
+ }
+}
+
+def GPRF16 : RegisterClass<"RISCV", [f16], 16, (add
+ (sequence "X%u", 10, 17),
+ (sequence "X%u", 5, 7),
+ (sequence "X%u", 28, 31),
+ (sequence "X%u", 8, 9),
+ (sequence "X%u", 18, 27),
+ (sequence "X%u", 0, 4)
+)> {
+ let RegInfos = XLenRI;
+}
+
+def GPRF32 : RegisterClass<"RISCV", [f32], 32, (add
+ (sequence "X%u", 10, 17),
+ (sequence "X%u", 5, 7),
+ (sequence "X%u", 28, 31),
+ (sequence "X%u", 8, 9),
+ (sequence "X%u", 18, 27),
+ (sequence "X%u", 0, 4)
+)> {
+ let RegInfos = XLenRI;
+}
+
+def GPRF64 : RegisterClass<"RISCV", [f64], 64, (add
+ (sequence "X%u", 10, 17),
+ (sequence "X%u", 5, 7),
+ (sequence "X%u", 28, 31),
+ (sequence "X%u", 8, 9),
+ (sequence "X%u", 18, 27),
+ (sequence "X%u", 0, 4)
+)> {
+ let RegInfos = XLenRI;
+}
+
+def GPRPF64 : RegisterClass<"RISCV", [f64], 64, (add
+ X10_PD, X12_PD, X14_PD, X16_PD,
+ X6_PD,
+ X28_PD, X30_PD,
+ X8_PD,
+ X18_PD, X20_PD, X22_PD, X24_PD, X26_PD,
+ X0_PD, X2_PD, X4_PD
+)> {
+ let RegInfos = XLenRI;
+}
+
// The register class is added for inline assembly for vector mask types.
def VM : VReg<VMaskVTs,
(add (sequence "V%u", 8, 31),
Index: llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
@@ -27,6 +27,22 @@
def riscv_fmv_x_anyexth
: SDNode<"RISCVISD::FMV_X_ANYEXTH", SDT_RISCVFMV_X_ANYEXTH>;
+//===----------------------------------------------------------------------===//
+// Zhinx and Zhinxmin
+//===----------------------------------------------------------------------===//
+
+def GPRF16Op : RegisterOperand<GPRF16> {
+ let ParserMatchClass = GPRAsFPR;
+ let DecoderMethod = "DecodeGPRRegisterClass";
+}
+
+def FPR16Op : RegisterOperand<FPR16>;
+
+def ZFH : ExtInfo<"", [HasStdExtZfh], FPR16Op>;
+def ZHINX : ExtInfo<"_INX", [HasStdExtZhinx], GPRF16Op, "RVZfinx">;
+
+defvar HINX = [ZFH, ZHINX];
+
//===----------------------------------------------------------------------===//
// Instructions
//===----------------------------------------------------------------------===//
@@ -40,33 +56,52 @@
def FSH : FPStore_r<0b001, "fsh", FPR16, WriteFST16>;
} // Predicates = [HasStdExtZfhmin]
-let Predicates = [HasStdExtZfh] in {
let SchedRW = [WriteFMA16, ReadFMA16, ReadFMA16, ReadFMA16] in {
-def FMADD_H : FPFMA_rrr_frm<OPC_MADD, 0b10, "fmadd.h", FPR16>;
-def FMSUB_H : FPFMA_rrr_frm<OPC_MSUB, 0b10, "fmsub.h", FPR16>;
-def FNMSUB_H : FPFMA_rrr_frm<OPC_NMSUB, 0b10, "fnmsub.h", FPR16>;
-def FNMADD_H : FPFMA_rrr_frm<OPC_NMADD, 0b10, "fnmadd.h", FPR16>;
+defm FMADD_H : FPFMA_rrr_frm_m<OPC_MADD, 0b10, "fmadd.h", HINX>;
+defm FMSUB_H : FPFMA_rrr_frm_m<OPC_MSUB, 0b10, "fmsub.h", HINX>;
+defm FNMSUB_H : FPFMA_rrr_frm_m<OPC_NMSUB, 0b10, "fnmsub.h", HINX>;
+defm FNMADD_H : FPFMA_rrr_frm_m<OPC_NMADD, 0b10, "fnmadd.h", HINX>;
+}
+
+let Predicates = [HasStdExtZfh] in {
+def : FPFMADynFrmAlias<FMADD_H, "fmadd.h", FPR16Op>;
+def : FPFMADynFrmAlias<FMSUB_H, "fmsub.h", FPR16Op>;
+def : FPFMADynFrmAlias<FNMSUB_H, "fnmsub.h", FPR16Op>;
+def : FPFMADynFrmAlias<FNMADD_H, "fnmadd.h", FPR16Op>;
+} // Predicates = [HasStdExtZfh]
+
+let Predicates = [HasStdExtZhinx] in {
+def : FPFMADynFrmAlias<FMADD_H_INX, "fmadd.h", GPRF16Op>;
+def : FPFMADynFrmAlias<FMSUB_H_INX, "fmsub.h", GPRF16Op>;
+def : FPFMADynFrmAlias<FNMSUB_H_INX, "fnmsub.h", GPRF16Op>;
+def : FPFMADynFrmAlias<FNMADD_H_INX, "fnmadd.h", GPRF16Op>;
+} // Predicates = [HasStdExtZhinx]
+
+let SchedRW = [WriteFALU16, ReadFALU16, ReadFALU16] in {
+defm FADD_H : FPALU_rr_frm_m<0b0000010, "fadd.h", HINX>;
+defm FSUB_H : FPALU_rr_frm_m<0b0000110, "fsub.h", HINX>;
}
+let SchedRW = [WriteFMul16, ReadFMul16, ReadFMul16] in
+defm FMUL_H : FPALU_rr_frm_m<0b0001010, "fmul.h", HINX>;
-def : FPFMADynFrmAlias<FMADD_H, "fmadd.h", FPR16>;
-def : FPFMADynFrmAlias<FMSUB_H, "fmsub.h", FPR16>;
-def : FPFMADynFrmAlias<FNMSUB_H, "fnmsub.h", FPR16>;
-def : FPFMADynFrmAlias<FNMADD_H, "fnmadd.h", FPR16>;
-
-def FADD_H : FPALU_rr_frm<0b0000010, "fadd.h", FPR16>,
- Sched<[WriteFALU16, ReadFALU16, ReadFALU16]>;
-def FSUB_H : FPALU_rr_frm<0b0000110, "fsub.h", FPR16>,
- Sched<[WriteFALU16, ReadFALU16, ReadFALU16]>;
-def FMUL_H : FPALU_rr_frm<0b0001010, "fmul.h", FPR16>,
- Sched<[WriteFMul16, ReadFMul16, ReadFMul16]>;
-def FDIV_H : FPALU_rr_frm<0b0001110, "fdiv.h", FPR16>,
- Sched<[WriteFDiv16, ReadFDiv16, ReadFDiv16]>;
-
-def : FPALUDynFrmAlias<FADD_H, "fadd.h", FPR16>;
-def : FPALUDynFrmAlias<FSUB_H, "fsub.h", FPR16>;
-def : FPALUDynFrmAlias<FMUL_H, "fmul.h", FPR16>;
-def : FPALUDynFrmAlias<FDIV_H, "fdiv.h", FPR16>;
+let SchedRW = [WriteFDiv16, ReadFDiv16, ReadFDiv16] in
+defm FDIV_H : FPALU_rr_frm_m<0b0001110, "fdiv.h", HINX>;
+let Predicates = [HasStdExtZfh] in {
+def : FPALUDynFrmAlias<FADD_H, "fadd.h", FPR16Op>;
+def : FPALUDynFrmAlias<FSUB_H, "fsub.h", FPR16Op>;
+def : FPALUDynFrmAlias<FMUL_H, "fmul.h", FPR16Op>;
+def : FPALUDynFrmAlias<FDIV_H, "fdiv.h", FPR16Op>;
+} // Predicates = [HasStdExtZfh]
+
+let Predicates = [HasStdExtZhinx] in {
+def : FPALUDynFrmAlias<FADD_H_INX, "fadd.h", GPRF16Op>;
+def : FPALUDynFrmAlias<FSUB_H_INX, "fsub.h", GPRF16Op>;
+def : FPALUDynFrmAlias<FMUL_H_INX, "fmul.h", GPRF16Op>;
+def : FPALUDynFrmAlias<FDIV_H_INX, "fdiv.h", GPRF16Op>;
+} // Predicates = [HasStdExtZhinx]
+
+let Predicates = [HasStdExtZfh] in {
def FSQRT_H : FPUnaryOp_r_frm<0b0101110, 0b00000, FPR16, FPR16, "fsqrt.h">,
Sched<[WriteFSqrt16, ReadFSqrt16]>;
def : FPUnaryOpDynFrmAlias<FSQRT_H, "fsqrt.h", FPR16, FPR16>;
Index: llvm/lib/Target/RISCV/RISCVInstrInfoF.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoF.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoF.td
@@ -55,6 +55,35 @@
// Operand and SDNode transformation definitions.
//===----------------------------------------------------------------------===//
+// Zfinx
+
+def GPRAsFPR : AsmOperandClass {
+ let Name = "GPRAsFPR";
+ let ParserMethod = "parseGPRAsFPR";
+ let RenderMethod = "addRegOperands";
+}
+
+def GPRF32Op : RegisterOperand<GPRF32> {
+ let ParserMatchClass = GPRAsFPR;
+ let DecoderMethod = "DecodeGPRRegisterClass";
+}
+
+def GPROp : RegisterOperand<GPR>;
+def FPR32Op : RegisterOperand<FPR32>;
+
+class ExtInfo<string suffix, list<Predicate> pres, RegisterOperand reg,
+ string space = ""> {
+ string Name = suffix;
+ list<Predicate> Predicates = pres;
+ RegisterOperand Reg = reg;
+ string Space = space;
+}
+
+def F : ExtInfo<"", [HasStdExtF], FPR32Op>;
+def ZFINX : ExtInfo<"_INX", [HasStdExtZfinx], GPRF32Op, "RVZfinx">;
+
+defvar FINX = [F, ZFINX];
+
// Floating-point rounding mode
def FRMArg : AsmOperandClass {
@@ -92,13 +121,21 @@
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1,
UseNamedOperandTable = 1, hasPostISelHook = 1 in
class FPFMA_rrr_frm<RISCVOpcode opcode, bits<2> funct2, string opcodestr,
- RegisterClass rty>
+ RegisterOperand rty>
: RVInstR4Frm<funct2, opcode, (outs rty:$rd),
(ins rty:$rs1, rty:$rs2, rty:$rs3, frmarg:$frm),
opcodestr, "$rd, $rs1, $rs2, $rs3, $frm">;
+multiclass FPFMA_rrr_frm_m<RISCVOpcode opcode, bits<2> funct2,
+ string opcodestr, list<ExtInfo> Exts> {
+ foreach Ext = Exts in {
+ let Predicates = Ext.Predicates, DecoderNamespace = Ext.Space in
+ def Ext.Name : FPFMA_rrr_frm<opcode, funct2, opcodestr, Ext.Reg>;
+ }
+}
+
class FPFMADynFrmAlias<FPFMA_rrr_frm Inst, string OpcodeStr,
- RegisterClass rty>
+ RegisterOperand rty>
: InstAlias<OpcodeStr#" $rd, $rs1, $rs2, $rs3",
(Inst rty:$rd, rty:$rs1, rty:$rs2, rty:$rs3, 0b111)>;
@@ -110,13 +147,20 @@
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1,
UseNamedOperandTable = 1, hasPostISelHook = 1 in
-class FPALU_rr_frm<bits<7> funct7, string opcodestr, RegisterClass rty>
+class FPALU_rr_frm<bits<7> funct7, string opcodestr, RegisterOperand rty>
: RVInstRFrm<funct7, OPC_OP_FP, (outs rty:$rd),
(ins rty:$rs1, rty:$rs2, frmarg:$frm), opcodestr,
"$rd, $rs1, $rs2, $frm">;
+multiclass FPALU_rr_frm_m<bits<7> funct7, string opcodestr, list<ExtInfo> Exts> {
+ foreach Ext = Exts in {
+ let Predicates = Ext.Predicates, DecoderNamespace = Ext.Space in
+ def Ext.Name : FPALU_rr_frm<funct7, opcodestr, Ext.Reg>;
+ }
+}
+
class FPALUDynFrmAlias<FPALU_rr_frm Inst, string OpcodeStr,
- RegisterClass rty>
+ RegisterOperand rty>
: InstAlias<OpcodeStr#" $rd, $rs1, $rs2",
(Inst rty:$rd, rty:$rs1, rty:$rs2, 0b111)>;
@@ -160,33 +204,54 @@
// reflecting the order these fields are specified in the instruction
// encoding.
def FSW : FPStore_r<0b010, "fsw", FPR32, WriteFST32>;
+} // Predicates = [HasStdExtF]
let SchedRW = [WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32] in {
-def FMADD_S : FPFMA_rrr_frm<OPC_MADD, 0b00, "fmadd.s", FPR32>;
-def FMSUB_S : FPFMA_rrr_frm<OPC_MSUB, 0b00, "fmsub.s", FPR32>;
-def FNMSUB_S : FPFMA_rrr_frm<OPC_NMSUB, 0b00, "fnmsub.s", FPR32>;
-def FNMADD_S : FPFMA_rrr_frm<OPC_NMADD, 0b00, "fnmadd.s", FPR32>;
+defm FMADD_S : FPFMA_rrr_frm_m<OPC_MADD, 0b00, "fmadd.s", FINX>;
+defm FMSUB_S : FPFMA_rrr_frm_m<OPC_MSUB, 0b00, "fmsub.s", FINX>;
+defm FNMSUB_S : FPFMA_rrr_frm_m<OPC_NMSUB, 0b00, "fnmsub.s", FINX>;
+defm FNMADD_S : FPFMA_rrr_frm_m<OPC_NMADD, 0b00, "fnmadd.s", FINX>;
}
-def : FPFMADynFrmAlias<FMADD_S, "fmadd.s", FPR32>;
-def : FPFMADynFrmAlias<FMSUB_S, "fmsub.s", FPR32>;
-def : FPFMADynFrmAlias<FNMSUB_S, "fnmsub.s", FPR32>;
-def : FPFMADynFrmAlias<FNMADD_S, "fnmadd.s", FPR32>;
-
-def FADD_S : FPALU_rr_frm<0b0000000, "fadd.s", FPR32>,
- Sched<[WriteFALU32, ReadFALU32, ReadFALU32]>;
-def FSUB_S : FPALU_rr_frm<0b0000100, "fsub.s", FPR32>,
- Sched<[WriteFALU32, ReadFALU32, ReadFALU32]>;
-def FMUL_S : FPALU_rr_frm<0b0001000, "fmul.s", FPR32>,
- Sched<[WriteFMul32, ReadFMul32, ReadFMul32]>;
-def FDIV_S : FPALU_rr_frm<0b0001100, "fdiv.s", FPR32>,
- Sched<[WriteFDiv32, ReadFDiv32, ReadFDiv32]>;
-
-def : FPALUDynFrmAlias<FADD_S, "fadd.s", FPR32>;
-def : FPALUDynFrmAlias<FSUB_S, "fsub.s", FPR32>;
-def : FPALUDynFrmAlias<FMUL_S, "fmul.s", FPR32>;
-def : FPALUDynFrmAlias<FDIV_S, "fdiv.s", FPR32>;
+let Predicates = [HasStdExtF] in {
+def : FPFMADynFrmAlias<FMADD_S, "fmadd.s", FPR32Op>;
+def : FPFMADynFrmAlias<FMSUB_S, "fmsub.s", FPR32Op>;
+def : FPFMADynFrmAlias<FNMSUB_S, "fnmsub.s", FPR32Op>;
+def : FPFMADynFrmAlias<FNMADD_S, "fnmadd.s", FPR32Op>;
+} // Predicates = [HasStdExtF]
+
+let Predicates = [HasStdExtZfinx] in {
+def : FPFMADynFrmAlias<FMADD_S_INX, "fmadd.s", GPRF32Op>;
+def : FPFMADynFrmAlias<FMSUB_S_INX, "fmsub.s", GPRF32Op>;
+def : FPFMADynFrmAlias<FNMSUB_S_INX, "fnmsub.s", GPRF32Op>;
+def : FPFMADynFrmAlias<FNMADD_S_INX, "fnmadd.s", GPRF32Op>;
+} // Predicates = [HasStdExtZfinx]
+
+let SchedRW = [WriteFALU32, ReadFALU32, ReadFALU32] in {
+defm FADD_S : FPALU_rr_frm_m<0b0000000, "fadd.s", FINX>;
+defm FSUB_S : FPALU_rr_frm_m<0b0000100, "fsub.s", FINX>;
+}
+let SchedRW = [WriteFMul32, ReadFMul32, ReadFMul32] in
+defm FMUL_S : FPALU_rr_frm_m<0b0001000, "fmul.s", FINX>;
+let SchedRW = [WriteFDiv32, ReadFDiv32, ReadFDiv32] in
+defm FDIV_S : FPALU_rr_frm_m<0b0001100, "fdiv.s", FINX>;
+
+let Predicates = [HasStdExtF] in {
+def : FPALUDynFrmAlias<FADD_S, "fadd.s", FPR32Op>;
+def : FPALUDynFrmAlias<FSUB_S, "fsub.s", FPR32Op>;
+def : FPALUDynFrmAlias<FMUL_S, "fmul.s", FPR32Op>;
+def : FPALUDynFrmAlias<FDIV_S, "fdiv.s", FPR32Op>;
+} // Predicates = [HasStdExtF]
+
+let Predicates = [HasStdExtZfinx] in {
+def : FPALUDynFrmAlias<FADD_S_INX, "fadd.s", GPRF32Op>;
+def : FPALUDynFrmAlias<FSUB_S_INX, "fsub.s", GPRF32Op>;
+def : FPALUDynFrmAlias<FMUL_S_INX, "fmul.s", GPRF32Op>;
+def : FPALUDynFrmAlias<FDIV_S_INX, "fdiv.s", GPRF32Op>;
+} // Predicates = [HasStdExtZfinx]
+
+let Predicates = [HasStdExtF] in {
def FSQRT_S : FPUnaryOp_r_frm<0b0101100, 0b00000, FPR32, FPR32, "fsqrt.s">,
Sched<[WriteFSqrt32, ReadFSqrt32]>;
def : FPUnaryOpDynFrmAlias<FSQRT_S, "fsqrt.s", FPR32, FPR32>;
Index: llvm/lib/Target/RISCV/RISCVInstrInfoD.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoD.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoD.td
@@ -25,6 +25,41 @@
def RISCVBuildPairF64 : SDNode<"RISCVISD::BuildPairF64", SDT_RISCVBuildPairF64>;
def RISCVSplitF64 : SDNode<"RISCVISD::SplitF64", SDT_RISCVSplitF64>;
+//===----------------------------------------------------------------------===//
+// Zdinx
+//===----------------------------------------------------------------------===//
+
+def GPRPF64AsFPR : AsmOperandClass {
+ let Name = "GPRPF64AsFPR";
+ let ParserMethod = "parseGPRAsFPR";
+ let RenderMethod = "addRegOperands";
+}
+
+def GPRF64AsFPR : AsmOperandClass {
+ let Name = "GPRF64AsFPR";
+ let ParserMethod = "parseGPRAsFPR";
+ let RenderMethod = "addRegOperands";
+}
+
+def GPRF64Op : RegisterOperand<GPRF64> {
+ let ParserMatchClass = GPRF64AsFPR;
+ let DecoderMethod = "DecodeGPRRegisterClass";
+}
+
+def GPRPF64Op : RegisterOperand<GPRPF64> {
+ let ParserMatchClass = GPRPF64AsFPR;
+}
+
+def FPR64Op : RegisterOperand<FPR64>;
+
+def D : ExtInfo<"", [HasStdExtD], FPR64Op>;
+def ZDINX : ExtInfo<"_INX", [HasStdExtZdinx, IsRV64], GPRF64Op,
+ "RVZfinx">;
+def ZDIN32X : ExtInfo<"_IN32X", [HasStdExtZdinx, IsRV32], GPRPF64Op,
+ "RV32Zdinx">;
+
+defvar DINX = [D, ZDINX, ZDIN32X];
+
//===----------------------------------------------------------------------===//
// Instructions
//===----------------------------------------------------------------------===//
@@ -36,33 +71,68 @@
// reflecting the order these fields are specified in the instruction
// encoding.
def FSD : FPStore_r<0b011, "fsd", FPR64, WriteFST64>;
+} // Predicates = [HasStdExtD]
let SchedRW = [WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64] in {
-def FMADD_D : FPFMA_rrr_frm<OPC_MADD, 0b01, "fmadd.d", FPR64>;
-def FMSUB_D : FPFMA_rrr_frm<OPC_MSUB, 0b01, "fmsub.d", FPR64>;
-def FNMSUB_D : FPFMA_rrr_frm<OPC_NMSUB, 0b01, "fnmsub.d", FPR64>;
-def FNMADD_D : FPFMA_rrr_frm<OPC_NMADD, 0b01, "fnmadd.d", FPR64>;
+defm FMADD_D : FPFMA_rrr_frm_m<OPC_MADD, 0b01, "fmadd.d", DINX>;
+defm FMSUB_D : FPFMA_rrr_frm_m<OPC_MSUB, 0b01, "fmsub.d", DINX>;
+defm FNMSUB_D : FPFMA_rrr_frm_m<OPC_NMSUB, 0b01, "fnmsub.d", DINX>;
+defm FNMADD_D : FPFMA_rrr_frm_m<OPC_NMADD, 0b01, "fnmadd.d", DINX>;
+}
+
+let Predicates = [HasStdExtD] in {
+def : FPFMADynFrmAlias<FMADD_D, "fmadd.d", FPR64Op>;
+def : FPFMADynFrmAlias<FMSUB_D, "fmsub.d", FPR64Op>;
+def : FPFMADynFrmAlias<FNMSUB_D, "fnmsub.d", FPR64Op>;
+def : FPFMADynFrmAlias<FNMADD_D, "fnmadd.d", FPR64Op>;
+} // Predicates = [HasStdExtD]
+
+let Predicates = [HasStdExtZdinx, IsRV64] in {
+def : FPFMADynFrmAlias<FMADD_D_INX, "fmadd.d", GPRF64Op>;
+def : FPFMADynFrmAlias<FMSUB_D_INX, "fmsub.d", GPRF64Op>;
+def : FPFMADynFrmAlias<FNMSUB_D_INX, "fnmsub.d", GPRF64Op>;
+def : FPFMADynFrmAlias<FNMADD_D_INX, "fnmadd.d", GPRF64Op>;
+} // Predicates = [HasStdExtZdinx]
+
+let Predicates = [HasStdExtZdinx, IsRV32] in {
+def : FPFMADynFrmAlias<FMADD_D_IN32X, "fmadd.d", GPRPF64Op>;
+def : FPFMADynFrmAlias<FMSUB_D_IN32X, "fmsub.d", GPRPF64Op>;
+def : FPFMADynFrmAlias<FNMSUB_D_IN32X, "fnmsub.d", GPRPF64Op>;
+def : FPFMADynFrmAlias<FNMADD_D_IN32X, "fnmadd.d", GPRPF64Op>;
+} // Predicates = [HasStdExtZdinx]
+
+let SchedRW = [WriteFALU64, ReadFALU64, ReadFALU64] in {
+defm FADD_D : FPALU_rr_frm_m<0b0000001, "fadd.d", DINX>;
+defm FSUB_D : FPALU_rr_frm_m<0b0000101, "fsub.d", DINX>;
}
+let SchedRW = [WriteFMul64, ReadFMul64, ReadFMul64] in
+defm FMUL_D : FPALU_rr_frm_m<0b0001001, "fmul.d", DINX>;
-def : FPFMADynFrmAlias<FMADD_D, "fmadd.d", FPR64>;
-def : FPFMADynFrmAlias<FMSUB_D, "fmsub.d", FPR64>;
-def : FPFMADynFrmAlias<FNMSUB_D, "fnmsub.d", FPR64>;
-def : FPFMADynFrmAlias<FNMADD_D, "fnmadd.d", FPR64>;
-
-def FADD_D : FPALU_rr_frm<0b0000001, "fadd.d", FPR64>,
- Sched<[WriteFALU64, ReadFALU64, ReadFALU64]>;
-def FSUB_D : FPALU_rr_frm<0b0000101, "fsub.d", FPR64>,
- Sched<[WriteFALU64, ReadFALU64, ReadFALU64]>;
-def FMUL_D : FPALU_rr_frm<0b0001001, "fmul.d", FPR64>,
- Sched<[WriteFMul64, ReadFMul64, ReadFMul64]>;
-def FDIV_D : FPALU_rr_frm<0b0001101, "fdiv.d", FPR64>,
- Sched<[WriteFDiv64, ReadFDiv64, ReadFDiv64]>;
-
-def : FPALUDynFrmAlias<FADD_D, "fadd.d", FPR64>;
-def : FPALUDynFrmAlias<FSUB_D, "fsub.d", FPR64>;
-def : FPALUDynFrmAlias<FMUL_D, "fmul.d", FPR64>;
-def : FPALUDynFrmAlias<FDIV_D, "fdiv.d", FPR64>;
+let SchedRW = [WriteFDiv64, ReadFDiv64, ReadFDiv64] in
+defm FDIV_D : FPALU_rr_frm_m<0b0001101, "fdiv.d", DINX>;
+let Predicates = [HasStdExtD] in {
+def : FPALUDynFrmAlias<FADD_D, "fadd.d", FPR64Op>;
+def : FPALUDynFrmAlias<FSUB_D, "fsub.d", FPR64Op>;
+def : FPALUDynFrmAlias<FMUL_D, "fmul.d", FPR64Op>;
+def : FPALUDynFrmAlias<FDIV_D, "fdiv.d", FPR64Op>;
+} // Predicates = [HasStdExtD]
+
+let Predicates = [HasStdExtZdinx, IsRV64] in {
+def : FPALUDynFrmAlias<FADD_D_INX, "fadd.d", GPRF64Op>;
+def : FPALUDynFrmAlias<FSUB_D_INX, "fsub.d", GPRF64Op>;
+def : FPALUDynFrmAlias<FMUL_D_INX, "fmul.d", GPRF64Op>;
+def : FPALUDynFrmAlias<FDIV_D_INX, "fdiv.d", GPRF64Op>;
+} // Predicates = [HasStdExtZdinx, IsRV64]
+
+let Predicates = [HasStdExtZdinx, IsRV32] in {
+def : FPALUDynFrmAlias<FADD_D_IN32X, "fadd.d", GPRPF64Op>;
+def : FPALUDynFrmAlias<FSUB_D_IN32X, "fsub.d", GPRPF64Op>;
+def : FPALUDynFrmAlias<FMUL_D_IN32X, "fmul.d", GPRPF64Op>;
+def : FPALUDynFrmAlias<FDIV_D_IN32X, "fdiv.d", GPRPF64Op>;
+} // Predicates = [HasStdExtZdinx, IsRV32]
+
+let Predicates = [HasStdExtD] in {
def FSQRT_D : FPUnaryOp_r_frm<0b0101101, 0b00000, FPR64, FPR64, "fsqrt.d">,
Sched<[WriteFSqrt64, ReadFSqrt64]>;
def : FPUnaryOpDynFrmAlias<FSQRT_D, "fsqrt.d", FPR64, FPR64>;
Index: llvm/lib/Target/RISCV/RISCV.td
===================================================================
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -57,6 +57,37 @@
AssemblerPredicate<(all_of FeatureStdExtZfh),
"'Zfh' (Half-Precision Floating-Point)">;
+def FeatureStdExtZfinx
+ : SubtargetFeature<"experimental-zfinx", "HasStdExtZfinx", "true",
+ "'Zfinx' (Float in Integer)">;
+def HasStdExtZfinx : Predicate<"Subtarget->hasStdExtZfinx()">,
+ AssemblerPredicate<(all_of FeatureStdExtZfinx),
+ "'Zfinx' (Float in Integer)">;
+
+def FeatureStdExtZdinx
+ : SubtargetFeature<"experimental-zdinx", "HasStdExtZdinx", "true",
+ "'Zdinx' (Double in Integer)",
+ [FeatureStdExtZfinx]>;
+def HasStdExtZdinx : Predicate<"Subtarget->hasStdExtZdinx()">,
+ AssemblerPredicate<(all_of FeatureStdExtZdinx),
+ "'Zdinx' (Double in Integer)">;
+
+def FeatureStdExtZhinxmin
+ : SubtargetFeature<"experimental-zhinxmin", "HasStdExtZhinxmin", "true",
+ "'Zhinxmin' (Half Float in Integer Minimal)",
+ [FeatureStdExtZfinx]>;
+def HasStdExtZhinxmin : Predicate<"Subtarget->hasStdExtZhinxmin()">,
+ AssemblerPredicate<(all_of FeatureStdExtZhinxmin),
+ "'Zhinxmin' (Half Float in Integer Minimal)">;
+
+def FeatureStdExtZhinx
+ : SubtargetFeature<"experimental-zhinx", "HasStdExtZhinx", "true",
+ "'Zhinx' (Half Float in Integer)",
+ [FeatureStdExtZhinxmin]>;
+def HasStdExtZhinx : Predicate<"Subtarget->hasStdExtZhinx()">,
+ AssemblerPredicate<(all_of FeatureStdExtZhinx),
+ "'Zhinx' (Half Float in Integer)">;
+
def FeatureStdExtC
: SubtargetFeature<"c", "HasStdExtC", "true",
"'C' (Compressed Instructions)">;
Index: llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
===================================================================
--- llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -161,6 +161,17 @@
return MCDisassembler::Success;
}
+static DecodeStatus DecodeGPRPF64RegisterClass(MCInst &Inst, uint64_t RegNo,
+ uint64_t Address,
+ const void *Decoder) {
+ if (RegNo >= 32 || RegNo & 1)
+ return MCDisassembler::Fail;
+
+ MCRegister Reg = RISCV::X0 + RegNo;
+ Inst.addOperand(MCOperand::createReg(Reg));
+ return MCDisassembler::Success;
+}
+
static DecodeStatus DecodeVRRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
@@ -427,6 +438,28 @@
return MCDisassembler::Fail;
}
Insn = support::endian::read32le(Bytes.data());
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtZdinx] &&
+ !STI.getFeatureBits()[RISCV::Feature64Bit]) {
+ LLVM_DEBUG(dbgs() << "Trying RV32Zdinx table (Double in Integer and"
+ "rv32)\n");
+ Result = decodeInstruction(DecoderTableRV32Zdinx32, MI, Insn, Address,
+ this, STI);
+ if (Result != MCDisassembler::Fail) {
+ Size = 4;
+ return Result;
+ }
+ }
+
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtZfinx]) {
+ LLVM_DEBUG(dbgs() << "Trying RVZfinx table (Float in Integer):\n");
+ // Calling the auto-generated decoder function.
+ Result = decodeInstruction(DecoderTableRVZfinx32, MI, Insn, Address, this,
+ STI);
+ if (Result != MCDisassembler::Fail) {
+ Size = 4;
+ return Result;
+ }
+ }
LLVM_DEBUG(dbgs() << "Trying RISCV32 table :\n");
Result = decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
Size = 4;
Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===================================================================
--- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -170,6 +170,7 @@
OperandMatchResultTy parseVTypeI(OperandVector &Operands);
OperandMatchResultTy parseMaskReg(OperandVector &Operands);
OperandMatchResultTy parseInsnDirectiveOpcode(OperandVector &Operands);
+ OperandMatchResultTy parseGPRAsFPR(OperandVector &Operands);
bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
@@ -273,6 +274,8 @@
bool IsRV64;
+ bool IsGPRAsFPR;
+
struct RegOp {
MCRegister RegNum;
};
@@ -344,6 +347,14 @@
RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg.RegNum);
}
+ bool isGPRAsFPR() const { return isGPR() && IsGPRAsFPR; }
+
+ bool isGPRPF64AsFPR() const {
+ return isGPR() && IsGPRAsFPR && !IsRV64 && !((Reg.RegNum - RISCV::X0) & 1);
+ }
+
+ bool isGPRF64AsFPR() const { return isGPR() && IsGPRAsFPR && IsRV64; }
+
static bool evaluateConstantImm(const MCExpr *Expr, int64_t &Imm,
RISCVMCExpr::VariantKind &VK) {
if (auto *RE = dyn_cast<RISCVMCExpr>(Expr)) {
@@ -802,12 +813,14 @@
}
static std::unique_ptr<RISCVOperand> createReg(unsigned RegNo, SMLoc S,
- SMLoc E, bool IsRV64) {
+ SMLoc E, bool IsRV64,
+ bool IsGPRAsFPR = false) {
auto Op = std::make_unique<RISCVOperand>(KindTy::Register);
Op->Reg.RegNum = RegNo;
Op->StartLoc = S;
Op->EndLoc = E;
Op->IsRV64 = IsRV64;
+ Op->IsGPRAsFPR = IsGPRAsFPR;
return Op;
}
@@ -1736,6 +1749,26 @@
return MatchOperand_Success;
}
+OperandMatchResultTy RISCVAsmParser::parseGPRAsFPR(OperandVector &Operands) {
+ switch (getLexer().getKind()) {
+ default:
+ return MatchOperand_NoMatch;
+ case AsmToken::Identifier:
+ StringRef Name = getLexer().getTok().getIdentifier();
+ MCRegister RegNo;
+ matchRegisterNameHelper(isRV32E(), RegNo, Name);
+
+ if (RegNo == RISCV::NoRegister)
+ return MatchOperand_NoMatch;
+ SMLoc S = getLoc();
+ SMLoc E = SMLoc::getFromPointer(S.getPointer() - 1);
+ getLexer().Lex();
+ Operands.push_back(RISCVOperand::createReg(
+ RegNo, S, E, isRV64(), !getSTI().hasFeature(RISCV::FeatureStdExtF)));
+ }
+ return MatchOperand_Success;
+}
+
OperandMatchResultTy
RISCVAsmParser::parseMemOpBaseReg(OperandVector &Operands) {
if (getLexer().isNot(AsmToken::LParen)) {
Index: llvm/lib/Support/RISCVISAInfo.cpp
===================================================================
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -65,6 +65,11 @@
{"zfhmin", RISCVExtensionVersion{0, 1}},
{"zfh", RISCVExtensionVersion{0, 1}},
+
+ {"zfinx", RISCVExtensionVersion{1, 0}},
+ {"zdinx", RISCVExtensionVersion{1, 0}},
+ {"zhinxmin", RISCVExtensionVersion{1, 0}},
+ {"zhinx", RISCVExtensionVersion{1, 0}},
};
static bool stripExperimentalPrefix(StringRef &Ext) {
@@ -282,6 +287,15 @@
if (ExtName == "i")
continue;
+ if (ExtName == "zdinx")
+ Features.push_back("+zfinx");
+ if (ExtName == "zhinxmin")
+ Features.push_back("+zfinx");
+ if (ExtName == "zhinx") {
+ Features.push_back("+zfinx");
+ Features.push_back("+zhinxmin");
+ }
+
if (ExtName == "zvlsseg") {
Features.push_back("+experimental-v");
Features.push_back("+experimental-zvlsseg");
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