tlively added inline comments.
================ Comment at: llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td:1141 +def : Pat<(vec.int_vt (vselect + (setolt (vec.vt (bitconvert V128:$rhs)), + (vec.vt (bitconvert V128:$lhs))), ---------------- aheejin wrote: > Sorry I asked this in person yesterday, but I don't think I quiet got it; why > is this only for the ordered comparison? And does pseudo-min/max mean > non-NaN-propagating? pseudo-min is defined as `b < a ? b : a` and pseudo-max is defined as `a < b ? b : a`. Both of these definitions use `<` as the float comparison operator, which for WebAssembly means OLT. For both pseudo-min and pseudo-max, if `a` or `b` is NaN, the comparison will be `false` and the result will be `a`. So when `a` is NaN but `b` is not, these instructions are NaN-propagating. But when `b` is NaN and `a` is not, these instructions are not NaN-propagating. In contrast, the normal min and max operations propagate NaNs in either operand position. ================ Comment at: llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td:1145-1149 +def : Pat<(vec.int_vt (vselect + (setolt (vec.vt (bitconvert V128:$lhs)), + (vec.vt (bitconvert V128:$rhs))), + V128:$rhs, V128:$lhs)), + (pmax $lhs, $rhs)>; ---------------- aheejin wrote: > Is it OK to change the return type? The source pattern's return type is an > int vector but the resulting instruction's type is a float vector. Yes, this is the final step of DAG selection and we are lowering the SDNodes to TargetSDNodes here, so typing no longer applies. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D106612/new/ https://reviews.llvm.org/D106612 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
