aheejin added inline comments.
================ Comment at: llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td:1141 +def : Pat<(vec.int_vt (vselect + (setolt (vec.vt (bitconvert V128:$rhs)), + (vec.vt (bitconvert V128:$lhs))), ---------------- Sorry I asked this in person yesterday, but I don't think I quiet got it; why is this only for the ordered comparison? And does pseudo-min/max mean non-NaN-propagating? ================ Comment at: llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td:1145-1149 +def : Pat<(vec.int_vt (vselect + (setolt (vec.vt (bitconvert V128:$lhs)), + (vec.vt (bitconvert V128:$rhs))), + V128:$rhs, V128:$lhs)), + (pmax $lhs, $rhs)>; ---------------- Is it OK to change the return type? The source pattern's return type is an int vector but the resulting instruction's type is a float vector. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D106612/new/ https://reviews.llvm.org/D106612 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
