quinnp added inline comments.
================ Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-sync.c:2 // RUN: %clang_cc1 -triple powerpc64-unknown-unknown \ -// RUN: -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s +// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s // RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \ ---------------- qiucf wrote: > Why change `pwr7` to `pwr8`? This was to match the testing convention for XL compatibility builtins of targeting pwr7 for big endian and pwr8 for little endian. However, I will not be changing the `sync` tests in this patch, I have reversed those changes and will be putting them into a different patch. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D103986/new/ https://reviews.llvm.org/D103986 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
