Conanap created this revision.
Herald added subscribers: steven.zhang, shchenz, jfb, kbarton, hiraditya,
nemanjai.
Conanap requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.
This patch implaments the atomic load and store builtins
for the PowerPC target, in order to have feature parody with
xlC on AIX.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D105236
Files:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-atomicLoadStore.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-atomicLoadStore-64-only.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-atomicLoadStore.ll
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-atomicLoadStore.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-atomicLoadStore.ll
@@ -0,0 +1,49 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-64
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-64
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN: -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-32
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-64
+
+declare i32 @llvm.ppc.lwarx(i8*)
+define dso_local signext i32 @test_lwarx(i32* readnone %a) local_unnamed_addr #0 {
+; CHECK-64-LABEL: test_lwarx:
+; CHECK-64: # %bb.0: # %entry
+; CHECK-64-NEXT: lwarx 3, 0, 3
+; CHECK-64-NEXT: extsw 3, 3
+; CHECK-64-NEXT: blr
+;
+; CHECK-32-LABEL: test_lwarx:
+; CHECK-32: # %bb.0: # %entry
+; CHECK-32-NEXT: lwarx 3, 0, 3
+; CHECK-32-NEXT: blr
+entry:
+ %0 = bitcast i32* %a to i8*
+ %1 = tail call i32 @llvm.ppc.lwarx(i8* %0)
+ ret i32 %1
+}
+
+declare i32 @llvm.ppc.stwcx(i8*, i32)
+define dso_local signext i32 @test_stwcx(i32* %a, i32 signext %b) local_unnamed_addr #0 {
+; CHECK-64-LABEL: test_stwcx:
+; CHECK-64: # %bb.0: # %entry
+; CHECK-64-NEXT: stwcx. 4, 0, 3
+; CHECK-64-NEXT: mfocrf 3, 128
+; CHECK-64-NEXT: srwi 3, 3, 28
+; CHECK-64-NEXT: extsw 3, 3
+; CHECK-64-NEXT: blr
+;
+; CHECK-32-LABEL: test_stwcx:
+; CHECK-32: # %bb.0: # %entry
+; CHECK-32-NEXT: stwcx. 4, 0, 3
+; CHECK-32-NEXT: mfocrf 3, 128
+; CHECK-32-NEXT: srwi 3, 3, 28
+; CHECK-32-NEXT: blr
+entry:
+ %0 = bitcast i32* %a to i8*
+ %1 = tail call i32 @llvm.ppc.stwcx(i8* %0, i32 %b)
+ ret i32 %1
+}
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-atomicLoadStore-64-only.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-atomicLoadStore-64-only.ll
@@ -0,0 +1,35 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK
+
+declare i64 @llvm.ppc.ldarx(i8*)
+define dso_local i64 @test_ldarx(i64* readnone %a) local_unnamed_addr #0 {
+; CHECK-LABEL: test_ldarx:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ldarx 3, 0, 3
+; CHECK-NEXT: blr
+entry:
+ %0 = bitcast i64* %a to i8*
+ %1 = tail call i64 @llvm.ppc.ldarx(i8* %0)
+ ret i64 %1
+}
+
+declare i32 @llvm.ppc.stdcx(i8*, i64)
+define dso_local i64 @test(i64* %a, i64 %b) local_unnamed_addr #0 {
+; CHECK-LABEL: test:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: stdcx. 4, 0, 3
+; CHECK-NEXT: mfocrf 3, 128
+; CHECK-NEXT: srwi 3, 3, 28
+; CHECK-NEXT: extsw 3, 3
+; CHECK-NEXT: blr
+entry:
+ %0 = bitcast i64* %a to i8*
+ %1 = tail call i32 @llvm.ppc.stdcx(i8* %0, i64 %b)
+ %conv = sext i32 %1 to i64
+ ret i64 %conv
+}
Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -2836,3 +2836,10 @@
def : Pat<(v2i64 (PPCvecinsertelt v2i64:$vDi, i64:$rA, (i64 i))),
(VINSD $vDi, !mul(i, 8), $rA)>;
}
+
+let Predicates = [HasP8Altivec] in {
+ def : Pat<(int_ppc_lwarx xoaddr:$dst),
+ (LWARX xoaddr:$dst)>;
+ def : Pat<(int_ppc_stwcx xoaddr:$dst, gprc:$A),
+ (STWCX gprc:$A, xoaddr:$dst)>;
+}
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -1720,3 +1720,10 @@
def SLBSYNC : XForm_0<31, 338, (outs), (ins), "slbsync", IIC_SprSLBSYNC, []>;
} // IsISA3_0
+
+let Predicates = [HasP8Altivec] in {
+ def : Pat<(int_ppc_stdcx xoaddr:$dst, g8rc:$A),
+ (STDCX g8rc:$A, xoaddr:$dst)>;
+ def : Pat<(int_ppc_ldarx xoaddr:$dst),
+ (LDARX xoaddr:$dst)>;
+}
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===================================================================
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1523,5 +1523,12 @@
Intrinsic<[],[],[]>;
def int_ppc_iospace_eieio : GCCBuiltin<"__builtin_ppc_iospace_eieio">,
Intrinsic<[],[],[]>;
+ def int_ppc_stdcx : GCCBuiltin<"__builtin_ppc_stdcx">,
+ Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i64_ty], [IntrWriteMem]>;
+ def int_ppc_stwcx : GCCBuiltin<"__builtin_ppc_stwcx">,
+ Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty], [IntrWriteMem]>;
+ def int_ppc_lwarx : GCCBuiltin<"__builtin_ppc_lwarx">,
+ Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrNoMem]>;
+ def int_ppc_ldarx : GCCBuiltin<"__builtin_ppc_ldarx">,
+ Intrinsic<[llvm_i64_ty], [llvm_ptr_ty], [IntrNoMem]>;
}
-
Index: clang/test/CodeGen/builtins-ppc-xlcompat-atomicLoadStore.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-atomicLoadStore.c
@@ -0,0 +1,38 @@
+// RUN: %clang_cc1 -triple=powerpc-unknown-aix -O2 -S -emit-llvm %s -o - | \
+// RUN: FileCheck %s --check-prefix=CHECK
+// RUN: %clang_cc1 -triple=powerpc64-unknown-aix -O2 -S -emit-llvm %s -o - | \
+// RUN: FileCheck %s --check-prefixes=CHECK,CHECK64
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-unknown -O2 -S -emit-llvm %s \
+// RUN: -o - | FileCheck %s --check-prefixes=CHECK,CHECK64
+// RUN: %clang_cc1 -triple=powerpc64-unknown-unknown -O2 -S -emit-llvm %s \
+// RUN: -o - | FileCheck %s --check-prefixes=CHECK,CHECK64
+
+int test_lwarx(volatile int* a) {
+ // CHECK: entry:
+ // CHECK: %0 = bitcast i32* %a to i8*
+ // CHECK: %1 = tail call i32 @llvm.ppc.lwarx(i8* %0)
+ return __lwarx(a);
+}
+// CHECK64: def
+int test_stwcx(volatile int* a, int val) {
+ // CHECK: entry:
+ // CHECK: %0 = bitcast i32* %a to i8*
+ // CHECK: %1 = tail call i32 @llvm.ppc.stwcx(i8* %0, i32 %val)
+ return __stwcx(a, val);
+}
+
+#ifdef __PPC64__
+long test_ldarx(volatile long* a) {
+ // CHECK64: entry:
+ // CHECK64: %0 = bitcast i64* %a to i8*
+ // CHECK64: %1 = tail call i64 @llvm.ppc.ldarx(i8* %0)
+ return __ldarx(a);
+}
+
+int test_stdcx(volatile long* addr, long val) {
+ // CHECK64: entry:
+ // CHECK64: %0 = bitcast i64* %addr to i8*
+ // CHECK64: %1 = tail call i32 @llvm.ppc.stdcx(i8* %0, i64 %val)
+ return __stdcx(addr, val);
+}
+#endif
Index: clang/lib/Basic/Targets/PPC.cpp
===================================================================
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -108,6 +108,10 @@
Builder.defineMacro("__fetch_and_orlp", "__builtin_ppc_fetch_and_orlp");
Builder.defineMacro("__fetch_and_swap", "__builtin_ppc_fetch_and_swap");
Builder.defineMacro("__fetch_and_swaplp", "__builtin_ppc_fetch_and_swaplp");
+ Builder.defineMacro("__ldarx", "__builtin_ppc_ldarx");
+ Builder.defineMacro("__lwarx", "__builtin_ppc_lwarx");
+ Builder.defineMacro("__stdcx", "__builtin_ppc_stdcx");
+ Builder.defineMacro("__stwcx", "__builtin_ppc_stwcx");
}
/// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
Index: clang/include/clang/Basic/BuiltinsPPC.def
===================================================================
--- clang/include/clang/Basic/BuiltinsPPC.def
+++ clang/include/clang/Basic/BuiltinsPPC.def
@@ -55,6 +55,10 @@
BUILTIN(__builtin_ppc_fetch_and_orlp, "ULiULiD*ULi", "")
BUILTIN(__builtin_ppc_fetch_and_swap, "UiUiD*Ui", "")
BUILTIN(__builtin_ppc_fetch_and_swaplp, "ULiULiD*ULi", "")
+BUILTIN(__builtin_ppc_ldarx, "LiLiD*", "")
+BUILTIN(__builtin_ppc_lwarx, "iiD*", "")
+BUILTIN(__builtin_ppc_stdcx, "iLiD*Li", "")
+BUILTIN(__builtin_ppc_stwcx, "iiD*i", "")
BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n")
_______________________________________________
cfe-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
