Author: Yaxun (Sam) Liu Date: 2021-05-01T09:02:55-04:00 New Revision: 0175999805cf05d91c8a127ebd8c9d54a640abe9
URL: https://github.com/llvm/llvm-project/commit/0175999805cf05d91c8a127ebd8c9d54a640abe9 DIFF: https://github.com/llvm/llvm-project/commit/0175999805cf05d91c8a127ebd8c9d54a640abe9.diff LOG: [AMDGPU] Add options -mamdgpu-ieee -mno-amdgpu-ieee AMDGPU backend need to know whether floating point opcodes that support exception flag gathering quiet and propagate signaling NaN inputs per IEEE754-2008, which is conveyed by a function attribute "amdgpu-ieee". "amdgpu-ieee"="false" turns this off. Without this function attribute backend assumes it is on for compute functions. -mamdgpu-ieee and -mno-amdgpu-ieee are added to Clang to control this function attribute. By default it is on. -mno-amdgpu-ieee requires -fno-honor-nans or equivalent. Reviewed by: Matt Arsenault Differential Revision: https://reviews.llvm.org/D77013 Added: clang/test/CodeGenOpenCL/amdgpu-ieee.cl Modified: clang/include/clang/Basic/CodeGenOptions.def clang/include/clang/Basic/DiagnosticDriverKinds.td clang/include/clang/Driver/Options.td clang/lib/CodeGen/TargetInfo.cpp clang/lib/Frontend/CompilerInvocation.cpp Removed: ################################################################################ diff --git a/clang/include/clang/Basic/CodeGenOptions.def b/clang/include/clang/Basic/CodeGenOptions.def index d30dca5b18dab..e0bfcf6ef3e4c 100644 --- a/clang/include/clang/Basic/CodeGenOptions.def +++ b/clang/include/clang/Basic/CodeGenOptions.def @@ -426,6 +426,11 @@ CODEGENOPT(PassByValueIsNoAlias, 1, 0) /// according to the field declaring type width. CODEGENOPT(AAPCSBitfieldWidth, 1, 1) +/// Sets the IEEE bit in the expected default floating point mode register. +/// Floating point opcodes that support exception flag gathering quiet and +/// propagate signaling NaN inputs per IEEE 754-2008 (AMDGPU Only) +CODEGENOPT(EmitIEEENaNCompliantInsts, 1, 1) + #undef CODEGENOPT #undef ENUM_CODEGENOPT #undef VALUE_CODEGENOPT diff --git a/clang/include/clang/Basic/DiagnosticDriverKinds.td b/clang/include/clang/Basic/DiagnosticDriverKinds.td index a2ffe1378cb6d..1ae0df3633b35 100644 --- a/clang/include/clang/Basic/DiagnosticDriverKinds.td +++ b/clang/include/clang/Basic/DiagnosticDriverKinds.td @@ -129,6 +129,8 @@ def err_drv_invalid_Xopenmp_target_with_args : Error< "invalid -Xopenmp-target argument: '%0', options requiring arguments are unsupported">; def err_drv_argument_only_allowed_with : Error< "invalid argument '%0' only allowed with '%1'">; +def err_drv_amdgpu_ieee_without_no_honor_nans : Error< + "invalid argument '-mno-amdgpu-ieee' only allowed with relaxed NaN handling">; def err_drv_argument_not_allowed_with : Error< "invalid argument '%0' not allowed with '%1'">; def err_drv_invalid_version_number : Error< diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index 8c9033ded10b6..a8a7177c82cc9 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -3177,6 +3177,14 @@ def mexec_model_EQ : Joined<["-"], "mexec-model=">, Group<m_wasm_Features_Driver Values<"command,reactor">, HelpText<"Execution model (WebAssembly only)">; +defm amdgpu_ieee : BoolOption<"m", "amdgpu-ieee", + CodeGenOpts<"EmitIEEENaNCompliantInsts">, DefaultTrue, + PosFlag<SetTrue, [], "Sets the IEEE bit in the expected default floating point " + " mode register. Floating point opcodes that support exception flag " + "gathering quiet and propagate signaling NaN inputs per IEEE 754-2008. " + "This option changes the ABI. (AMDGPU only)">, + NegFlag<SetFalse, [CC1Option]>>, Group<m_Group>; + def mcode_object_version_EQ : Joined<["-"], "mcode-object-version=">, Group<m_Group>, HelpText<"Specify code object ABI version. Defaults to 3. (AMDGPU only)">, MetaVarName<"<version>">, Values<"2,3,4">; diff --git a/clang/lib/CodeGen/TargetInfo.cpp b/clang/lib/CodeGen/TargetInfo.cpp index 52dce97605ea9..9577b61ca6d00 100644 --- a/clang/lib/CodeGen/TargetInfo.cpp +++ b/clang/lib/CodeGen/TargetInfo.cpp @@ -9166,6 +9166,9 @@ void AMDGPUTargetCodeGenInfo::setTargetAttributes( if (M.getContext().getTargetInfo().allowAMDGPUUnsafeFPAtomics()) F->addFnAttr("amdgpu-unsafe-fp-atomics", "true"); + + if (!getABIInfo().getCodeGenOpts().EmitIEEENaNCompliantInsts) + F->addFnAttr("amdgpu-ieee", "false"); } unsigned AMDGPUTargetCodeGenInfo::getOpenCLKernelCallingConv() const { diff --git a/clang/lib/Frontend/CompilerInvocation.cpp b/clang/lib/Frontend/CompilerInvocation.cpp index 2578c8cc0b952..b3e1e06bf8a25 100644 --- a/clang/lib/Frontend/CompilerInvocation.cpp +++ b/clang/lib/Frontend/CompilerInvocation.cpp @@ -1944,6 +1944,11 @@ bool CompilerInvocation::ParseCodeGenArgs(CodeGenOptions &Opts, ArgList &Args, else if (Args.hasArg(options::OPT_fno_finite_loops)) Opts.FiniteLoops = CodeGenOptions::FiniteLoopsKind::Never; + Opts.EmitIEEENaNCompliantInsts = + Args.hasFlag(options::OPT_mamdgpu_ieee, options::OPT_mno_amdgpu_ieee); + if (!Opts.EmitIEEENaNCompliantInsts && !LangOptsRef.NoHonorNaNs) + Diags.Report(diag::err_drv_amdgpu_ieee_without_no_honor_nans); + return Diags.getNumErrors() == NumErrorsBefore; } diff --git a/clang/test/CodeGenOpenCL/amdgpu-ieee.cl b/clang/test/CodeGenOpenCL/amdgpu-ieee.cl new file mode 100644 index 0000000000000..0a7b0d4f494ef --- /dev/null +++ b/clang/test/CodeGenOpenCL/amdgpu-ieee.cl @@ -0,0 +1,47 @@ +// REQUIRES: amdgpu-registered-target +// +// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -O0 -emit-llvm -o - %s \ +// RUN: | FileCheck -check-prefixes=COMMON,ON %s +// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -O0 -emit-llvm -o - %s \ +// RUN: -mno-amdgpu-ieee -menable-no-nans \ +// RUN: | FileCheck -check-prefixes=COMMON,OFF %s +// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -O0 -emit-llvm -o - %s \ +// RUN: -mno-amdgpu-ieee -cl-fast-relaxed-math \ +// RUN: | FileCheck -check-prefixes=COMMON,OFF %s + +// Check AMDGCN ISA generation. + +// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -O3 -S -o - %s \ +// RUN: | FileCheck -check-prefixes=ISA-ON %s +// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -O3 -S -o - %s \ +// RUN: -mno-amdgpu-ieee -menable-no-nans \ +// RUN: | FileCheck -check-prefixes=ISA-OFF %s + +// Check diagnostics when using -mno-amdgpu-ieee without NoHonorNaNs. + +// RUN: not %clang_cc1 -triple amdgcn-amd-amdhsa -O0 -emit-llvm -o - %s \ +// RUN: -mno-amdgpu-ieee 2>&1 | FileCheck -check-prefixes=DIAG %s + +// COMMON: define{{.*}} amdgpu_kernel void @kern{{.*}} [[ATTRS1:#[0-9]+]] +// ISA-ON: v_mul_f32_e64 v{{[0-9]+}}, 1.0, s{{[0-9]+}} +// ISA-ON: v_mul_f32_e64 v{{[0-9]+}}, 1.0, s{{[0-9]+}} +// ISA-ON: v_min_f32_e32 +// ISA-ON: ; IeeeMode: 1 +// ISA-OFF-NOT: v_mul_f32_e64 v{{[0-9]+}}, 1.0, s{{[0-9]+}} +// ISA-OFF-NOT: v_mul_f32_e64 v{{[0-9]+}}, 1.0, s{{[0-9]+}} +// ISA-OFF: v_min_f32_e32 +// ISA-OFF: ; IeeeMode: 0 +kernel void kern(global float *x, float y, float z) { + *x = __builtin_fmin(y, z); +} + +// COMMON: define{{.*}}void @fun() [[ATTRS2:#[0-9]+]] +void fun() { +} + +// ON-NOT: attributes [[ATTRS1]] = {{.*}} "amdgpu-ieee" +// OFF: attributes [[ATTRS1]] = {{.*}} "amdgpu-ieee"="false"{{.*}}"no-nans-fp-math"="true"{{.*}}"no-trapping-math"="true" +// ON-NOT: attributes [[ATTRS2]] = {{.*}} "amdgpu-ieee" +// OFF: attributes [[ATTRS2]] = {{.*}} "amdgpu-ieee"="false"{{.*}}"no-nans-fp-math"="true"{{.*}}"no-trapping-math"="true" + +// DIAG: invalid argument '-mno-amdgpu-ieee' only allowed with relaxed NaN handling _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
