This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG944adbf28550: Recommit "[RISCV] Add IR intrinsic for
Zbb extension" (authored by LevyHsu, committed by craig.topper).
Changed prior to commit:
https://reviews.llvm.org/D99320?vs=334322&id=335001#toc
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D99320/new/
https://reviews.llvm.org/D99320
Files:
clang/include/clang/Basic/BuiltinsRISCV.def
clang/include/clang/Basic/DiagnosticSemaKinds.td
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
llvm/include/llvm/IR/IntrinsicsRISCV.td
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoB.td
llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll
llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll
Index: llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll
@@ -0,0 +1,37 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
+; RUN: | FileCheck %s -check-prefix=RV64IB
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb -verify-machineinstrs < %s \
+; RUN: | FileCheck %s -check-prefix=RV64IBB
+
+declare i32 @llvm.riscv.orc.b.i32(i32)
+
+define i32 @orcb32(i32 %a) nounwind {
+; RV64IB-LABEL: orcb32:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: orc.b a0, a0
+; RV64IB-NEXT: ret
+;
+; RV64IBB-LABEL: orcb32:
+; RV64IBB: # %bb.0:
+; RV64IBB-NEXT: orc.b a0, a0
+; RV64IBB-NEXT: ret
+ %tmp = call i32 @llvm.riscv.orc.b.i32(i32 %a)
+ ret i32 %tmp
+}
+
+declare i64 @llvm.riscv.orc.b.i64(i64)
+
+define i64 @orcb64(i64 %a) nounwind {
+; RV64IB-LABEL: orcb64:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: orc.b a0, a0
+; RV64IB-NEXT: ret
+;
+; RV64IBB-LABEL: orcb64:
+; RV64IBB: # %bb.0:
+; RV64IBB-NEXT: orc.b a0, a0
+; RV64IBB-NEXT: ret
+ %tmp = call i64 @llvm.riscv.orc.b.i64(i64 %a)
+ ret i64 %tmp
+}
Index: llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll
@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-b -verify-machineinstrs < %s \
+; RUN: | FileCheck %s -check-prefix=RV32IB
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb -verify-machineinstrs < %s \
+; RUN: | FileCheck %s -check-prefix=RV32IBB
+
+declare i32 @llvm.riscv.orc.b.i32(i32)
+
+define i32 @orcb(i32 %a) nounwind {
+; RV32IB-LABEL: orcb:
+; RV32IB: # %bb.0:
+; RV32IB-NEXT: orc.b a0, a0
+; RV32IB-NEXT: ret
+;
+; RV32IBB-LABEL: orcb:
+; RV32IBB: # %bb.0:
+; RV32IBB-NEXT: orc.b a0, a0
+; RV32IBB-NEXT: ret
+ %tmp = call i32 @llvm.riscv.orc.b.i32(i32 %a)
+ ret i32 %tmp
+}
Index: llvm/lib/Target/RISCV/RISCVInstrInfoB.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -894,6 +894,10 @@
(PACKUW GPR:$rs1, GPR:$rs2)>;
} // Predicates = [HasStdExtZbp, IsRV64]
+let Predicates = [HasStdExtZbb] in {
+def : PatGpr<int_riscv_orc_b, ORCB>;
+} // Predicates = [HasStdExtZbb]
+
let Predicates = [HasStdExtZbr] in {
def : PatGpr<int_riscv_crc32_b, CRC32B>;
def : PatGpr<int_riscv_crc32_h, CRC32H>;
Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -198,6 +198,9 @@
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
}
+ if (Subtarget.hasStdExtZbb() && Subtarget.is64Bit())
+ setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i32, Custom);
+
if (Subtarget.is64Bit()) {
setOperationAction(ISD::ADD, MVT::i32, Custom);
setOperationAction(ISD::SUB, MVT::i32, Custom);
@@ -4198,6 +4201,14 @@
default:
llvm_unreachable(
"Don't know how to custom type legalize this intrinsic!");
+ case Intrinsic::riscv_orc_b: {
+ SDValue Newop1 =
+ DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1));
+ SDValue Res =
+ DAG.getNode(N->getOpcode(), DL, MVT::i64, N->getOperand(0), Newop1);
+ Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
+ return;
+ }
case Intrinsic::riscv_vmv_x_s: {
EVT VT = N->getValueType(0);
MVT XLenVT = Subtarget.getXLenVT();
Index: llvm/include/llvm/IR/IntrinsicsRISCV.td
===================================================================
--- llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -10,28 +10,6 @@
//
//===----------------------------------------------------------------------===//
-//===----------------------------------------------------------------------===//
-// RISC-V Bitmanip (Bit Manipulation) Extension
-// Zbr extension part
-
-let TargetPrefix = "riscv" in {
-
- class BitMan_GPR_Intrinsics
- : Intrinsic<[llvm_any_ty],
- [LLVMMatchType<0>],
- [IntrNoMem, IntrSpeculatable, IntrWillReturn]>;
-
- def int_riscv_crc32_b : BitMan_GPR_Intrinsics;
- def int_riscv_crc32_h : BitMan_GPR_Intrinsics;
- def int_riscv_crc32_w : BitMan_GPR_Intrinsics;
- def int_riscv_crc32_d : BitMan_GPR_Intrinsics;
- def int_riscv_crc32c_b : BitMan_GPR_Intrinsics;
- def int_riscv_crc32c_h : BitMan_GPR_Intrinsics;
- def int_riscv_crc32c_w : BitMan_GPR_Intrinsics;
- def int_riscv_crc32c_d : BitMan_GPR_Intrinsics;
-
-} // TargetPrefix = "riscv"
-
//===----------------------------------------------------------------------===//
// Atomics
@@ -89,6 +67,30 @@
} // TargetPrefix = "riscv"
+//===----------------------------------------------------------------------===//
+// Bitmanip (Bit Manipulation) Extension
+
+let TargetPrefix = "riscv" in {
+
+ class BitManipGPRIntrinsics
+ : Intrinsic<[llvm_any_ty],
+ [LLVMMatchType<0>],
+ [IntrNoMem, IntrSpeculatable, IntrWillReturn]>;
+
+ // Zbb
+ def int_riscv_orc_b : BitManipGPRIntrinsics;
+
+ // Zbr
+ def int_riscv_crc32_b : BitManipGPRIntrinsics;
+ def int_riscv_crc32_h : BitManipGPRIntrinsics;
+ def int_riscv_crc32_w : BitManipGPRIntrinsics;
+ def int_riscv_crc32_d : BitManipGPRIntrinsics;
+ def int_riscv_crc32c_b : BitManipGPRIntrinsics;
+ def int_riscv_crc32c_h : BitManipGPRIntrinsics;
+ def int_riscv_crc32c_w : BitManipGPRIntrinsics;
+ def int_riscv_crc32c_d : BitManipGPRIntrinsics;
+} // TargetPrefix = "riscv"
+
//===----------------------------------------------------------------------===//
// Vectors
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
@@ -0,0 +1,27 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-zbb -emit-llvm %s -o - \
+// RUN: | FileCheck %s -check-prefix=RV64ZBB
+
+// RV64ZBB-LABEL: @orc_b_32(
+// RV64ZBB-NEXT: entry:
+// RV64ZBB-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBB-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV64ZBB-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV64ZBB-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.orc.b.i32(i32 [[TMP0]])
+// RV64ZBB-NEXT: ret i32 [[TMP1]]
+//
+int orc_b_32(int a) {
+ return __builtin_riscv_orc_b_32(a);
+}
+
+// RV64ZBB-LABEL: @orc_b_64(
+// RV64ZBB-NEXT: entry:
+// RV64ZBB-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBB-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBB-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBB-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.orc.b.i64(i64 [[TMP0]])
+// RV64ZBB-NEXT: ret i64 [[TMP1]]
+//
+long orc_b_64(long a) {
+ return __builtin_riscv_orc_b_64(a);
+}
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
@@ -0,0 +1,15 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-zbb -emit-llvm %s -o - \
+// RUN: | FileCheck %s -check-prefix=RV32ZBB
+
+// RV32ZBB-LABEL: @orc_b_32(
+// RV32ZBB-NEXT: entry:
+// RV32ZBB-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBB-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV32ZBB-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV32ZBB-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.orc.b.i32(i32 [[TMP0]])
+// RV32ZBB-NEXT: ret i32 [[TMP1]]
+//
+int orc_b_32(int a) {
+ return __builtin_riscv_orc_b_32(a);
+}
Index: clang/lib/Sema/SemaChecking.cpp
===================================================================
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3424,7 +3424,7 @@
for (auto &I : ReqFeatures) {
if (TI.hasFeature(I))
continue;
- // Make message like "experimental-zbr" to "Zbr"
+ // Convert features like "zbr" and "experimental-zbr" to "Zbr".
I.consume_front("experimental-");
std::string FeatureStr = I.str();
FeatureStr[0] = std::toupper(FeatureStr[0]);
Index: clang/lib/CodeGen/CGBuiltin.cpp
===================================================================
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -17877,6 +17877,13 @@
switch (BuiltinID) {
#include "clang/Basic/riscv_vector_builtin_cg.inc"
+ // Zbb
+ case RISCV::BI__builtin_riscv_orc_b_32:
+ case RISCV::BI__builtin_riscv_orc_b_64:
+ ID = Intrinsic::riscv_orc_b;
+ IntrinsicTypes = {ResultType};
+ break;
+
// Zbr
case RISCV::BI__builtin_riscv_crc32_b:
ID = Intrinsic::riscv_crc32_b;
@@ -17910,10 +17917,8 @@
ID = Intrinsic::riscv_crc32c_d;
IntrinsicTypes = {ResultType};
break;
- default: {
+ default:
llvm_unreachable("unexpected builtin ID");
- return nullptr;
- } // default
}
assert(ID != Intrinsic::not_intrinsic);
Index: clang/include/clang/Basic/DiagnosticSemaKinds.td
===================================================================
--- clang/include/clang/Basic/DiagnosticSemaKinds.td
+++ clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -11187,5 +11187,5 @@
// RISC-V builtin required extension warning
def err_riscv_builtin_requires_extension : Error<
- "builtin requires %0 extension support to be enabled">;
+ "builtin requires '%0' extension support to be enabled">;
} // end of sema component.
Index: clang/include/clang/Basic/BuiltinsRISCV.def
===================================================================
--- clang/include/clang/Basic/BuiltinsRISCV.def
+++ clang/include/clang/Basic/BuiltinsRISCV.def
@@ -17,6 +17,10 @@
#include "clang/Basic/riscv_vector_builtins.inc"
+// Zbb extension
+TARGET_BUILTIN(__builtin_riscv_orc_b_32, "ZiZi", "nc", "experimental-zbb")
+TARGET_BUILTIN(__builtin_riscv_orc_b_64, "WiWi", "nc", "experimental-zbb")
+
// Zbr extension
TARGET_BUILTIN(__builtin_riscv_crc32_b, "LiLi", "nc", "experimental-zbr")
TARGET_BUILTIN(__builtin_riscv_crc32_h, "LiLi", "nc", "experimental-zbr")
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