fpallares added inline comments.
================
Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:2367
+ Opcode == RISCV::VADC_VIM || Opcode == RISCV::VSBC_VVM ||
+ Opcode == RISCV::VSBC_VXM) {
+ if (DestReg == RISCV::V0)
----------------
I think we might not need to treat `vadc` and `vsbc` specially here. Since
those have 4 operands they should fall on the `else` branch of the next
`if-else` block:
```
if (Inst.getNumOperands() == 4)
CheckReg = Inst.getOperand(3).getReg();
```
And that should produce the expected result. Did I miss some other reason why
those should be treated separately?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D80802/new/
https://reviews.llvm.org/D80802
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