fpallares added a comment. Apologies we didn't identify this earlier but with the change of the mask register layout (`MLEN=1`) the overlap constraints involving the mask register were modified:
//**RVV-0.8, Section 5.3. Vector Masking:**// > The destination vector register group for a masked vector instruction can > only overlap the source mask register (v0) when LMUL=1. Otherwise, an illegal > instruction exception is raised. //**RVV-0.9, Section 5.3. Vector Masking:**// > The destination vector register group for a masked vector instruction cannot > overlap the source mask register (v0), unless the destination vector register > is being written with a mask value (e.g., comparisons) or the scalar result > of a reduction. Otherwise, an illegal instruction exception is raised. The change was introduced in this commit <https://github.com/riscv/riscv-v-spec/commit/9a77e128b5e96ca984ad50b7cd9330c841321efb>. From my understanding, with this change an instruction such as the following should be rejected in RVV-0.9: vadd.vv v0, v1, v2, v0.t Also note that `vadc`/`vsbc` already have this behaviour. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D80802/new/ https://reviews.llvm.org/D80802 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
