labrinea added inline comments.
================
Comment at: test/CodeGen/aarch64-v8.1a-neon-intrinsics.c:4
@@ -3,4 +3,3 @@
// RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon \
-// RUN: -target-feature +v8.1a -O3 -S -o - %s \
-// RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AARCH64
+// RUN: -target-feature +v8.1a -O1 -S -emit-llvm -o - %s | FileCheck %s
----------------
echristo wrote:
> Why do you need to enable the optimizers?
Our intention with these tests is to check that we are generating a sequence of
{v/s}qrdmulh, {v/s}q{add/sub}{s}, shufflevector, {insert/extract}element IR
instructions. Using -O1 promotes memory to registers, combines instructions,
and therefore decreases the context of IR that we need to check.
http://reviews.llvm.org/D15223
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