On 10/31/24 19:02, Jon Elson via cctalk wrote:
On 10/31/24 09:35, Donald Whittemore via cctalk wrote:
If I remember right I was told back in the early 70s by our IBM CE
that physical damage could be done to our model 30 or 40 if we ran a
program that did an Assembler instruction, B * For those
non-Assembler people that is an instruction to branch to the location
of the instruction. I think it might have caused a heat problem in
the core or CCROS or TROS.
Possible? Or is my 76 year old brain hallucinating?
Hammering a single location in core could overheat the select wires,
the individual cores or the select driver cards. I can believe this
could happen. I seriously doubt it could harm the CCROS or TROS. The
model 30 was SLOW, the original version (first 1000 machines) had a
2.5 us memory cycle time. But, a B instruction occupied 4 bytes. And
the model 30 memory was ONE SINGLE BYTE wide! So, it would have to
access 4 consecutive bytes over a 10 us period to read the entire
instruction. This would involve t different select wires in one axis,
but likely the same wire in the other axis.
On the model 40, memory was 16 bits wide, so it would still have to
access 2 consecutive words.
Anyway, I was told that on a model 40 (I think) that if you pressed
and held stop, system reset, and load simultaneously, it would pop a
component on a circuit card in the machine.
Jon
The Microdata 1600 8k memory boards, and sometimes the 16k core they had
would do bad things with continuous half cycle reads.
The full cycle was 1ms long and could heat up the resistors, but when
you did the half cycle reads it was only 600ns long continuous and could
damage the system core.
It was used for rippling moves up or down of strings where you'd read a
byte from somewhere in core and write it elsewhere with a pointer
increment in between.
The 1600 was microprogrammed, so there were no machine (macro level)
instructions to do damage, so the implementer of the machine language
microcode would have had to do the deed to damage the core.
Or one could do it from the front panel, as one could execute micro
instructions there in 'run" at full speed (200ns) speed. There was a
processor delay if you did reads like that which, so the speed would be
600ns back to back.
We had a 360/50 with both 512k internal processor core and an LCS of
1mb, and neither had any restrictions on such instructions, though I
don't think I know if there were hardware protections like others in
this thread are suggesting.
thanks
Jim
