Even earlier than the TPU on the 68332 is the communications
co-processor built into the 68302. This predate the entire CPU-32 family.
On 6/13/2024 10:56 AM, Adrian Godwin via cctalk wrote:
Even without things like system management mode, there are lots of speed-up
features on modern processors that result in variable execution times -
things like caching and pipelining. With sufficient care these can
sometimes be made predictable but there are certain common needs that
have always found it better to have a dedicated peripheral to do these
jobs.
The first common one was possibly the Motorola TPU (time processing unit)
on the 68332 and others. The target application was injection timing for
automotive ECUs and although external dedicated logic such as FPGAs have
also been used, the microprogrammable peripheral has continued to be a
feature of some relatively common processors. The TI processor in the
beaglebone has PRIs, the raspberry pi Pico RP2040 has PIOs, and there's
also the parallax propellor which has 8 high speed parallel processors
running at 80MHz and able to interleave operations on common ports : a
newer version has iirc a 1Ghz clock.
Another technique has 'abused' dma and serial data peripherals on esp8266,
esp32 and Teensy processors to produce pulse trains for WS2812 LED control
at IIS clock rates. They construct the desired output waveform in memory
and DMA them out, though this may be unsuitable for servo control as the
buffers are large, giving good precision but poor latency.
On Thu, Jun 13, 2024 at 4:40 PM Jon Elson via cctalk <[email protected]>
wrote:
On 6/12/24 09:52, Jon Elson via cctalk wrote:
On 6/12/24 03:02, Peter Corlett via cctalk wrote:
Fun factoid: despite modern x86 being clocked ~1000x
faster than ye olde
6502, there's not much in it between them when it comes
to interrupt
response time. If all goes well, x86 takes "only" a
hundred-ish cycles to do
its book-keeping and jump to the ISR, but if SMM is
active (spoiler: it
always is and you can't turn it off) then it introduces a
massive amount of
extra jitter and all bets are off.
Well, actually the Pentium classic was supposedly designed
as the flight computer for the F-15, and had VERY good
interrupt response time of around 5 us. We know all about
this as we used it with real time Linux in CNC motion
control systems. A big concern was what was the delay and
jitter from the RTC triggering an interrupt to when the
servo position counters were read. It has been a struggle
to maintain this level of low jitter with newer
processors, but we have found quite a few that can do it.
AACK! Sorry, that was supposed to be F-16!
Jon
