> On Sep 23, 2022, at 5:49 PM, Chuck Guzis via cctalk <cctalk@classiccmp.org>
> wrote:
>
> On 9/23/22 13:47, Fred Cisin via cctalk wrote:
>
>> It was useful as a simple test of whether an applicant had any
>> bit-twiddling experience. But, I couldn't think of practical application.
>>
>
> The 6600 implemented it (IIRC) as a tree of 8 bit adders. If you
> haven't read Jim Thornton's "Design of a Computer--The CDC 6600", you
> owe it to yourself to look it up:
>
> http://archive.computerhistory.org/resources/text/CDC/cdc.6600.thornton.design_of_a_computer_the_control_data_6600.1970.102630394.pdf
Roughly that, though it's more refined than that. It starts with 15 4-bit
population count circuits. Then those counts are summed in a tree consisting
of 8 3-bit adders feeding 4 4-bit adders feeding 2 5-bit adders and finally a
single 6-bit adder. There are latches at each stage, clocked 75 ns apart to
deliver the result in 400 ns (including overhead into and out of the functional
unit).
Thornton is nice for a superficial view of the machine, enough for a first
impression that's largely accurate. To see the full details, the "Block
Diagram" manuals, which can be found on Bitsavers, are amazing resources. For
example, while Thornton's famous "barrel" picture is a good conceptual model of
the PPU design, the actual details of how the barrel operates are a whole lot
more complex than that simple picture suggests. The block diagram spells it
all out in full.
paul
