I specifically said 74x74. Early TTL flipflops were very crude by comparison.
On Sun, May 15, 2022, 13:03 Brent Hilpert via cctalk <cctalk@classiccmp.org> wrote: > On 2022-May-15, at 1:16 AM, Eric Smith via cctalk wrote: > > On Sat, May 14, 2022, 16:09 ben via cctalk <cctalk@classiccmp.org> > wrote: > >> On 2022-05-14 11:50 a.m., Nigel Johnson Ham via cctalk wrote: > >>> AFAIR LS can only drive one unit TTL load. > >>>> paul > >> LS is 4 TTL, 4 ma low. > >> Was there a trick of forcing the output of D flip flip > >> to clear it? I was wondering if this is what kills all > >> the 7474's? > > > > I don't think that worked on any TTL (or CMOS) 74x74 flip flops, except > > maybe by accident if you shorted the output enough to draw Vcc down (or > > ground up) enough to disrupt the FF, and then you have other problems. > > > > Despite the logic diagram showing feedback from the outputs, all 74x74 > have > > buffered outputs. > > Per TI schematics from 1969: 74 standard, H and L series flip-flops are > unbuffered. Or at least many of them are/were, in their then-original form. > Including 7475, 7490, etc. The output transistors connect both to the pins > and wrap back to form the FF or other purposes. > > Collector-triggering was discussed a some years ago on the list in regards > to a pdp8 front panel where DEC used collector-triggering on 74175's (IMO, > bad design practice). From (my) empirical tests at the time, it turned out > some 74S (Schottky) parts could be collector-triggered. However, between > standard, LS, and S types, behaviour could vary with manufacturer and > production date. > > > > The recent TI data sheets show an equivalent schematic > > only for the 74LS74. I can't at the moment find one for the 7474. > > > It seems likely to me that early pre-TTL logic families like RTL might > have > > had FFs with unbuffered outputs, but I haven't checked. > >
